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PDF LXT334 Data sheet ( Hoja de datos )
| Número de pieza | LXT334 | |
| Descripción | Quad Short Haul Transceiver | |
| Fabricantes | Intel | |
| Logotipo |  |
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LXT334
Quad Short-Haul Transceiver with Clock Recovery
Datasheet
The LXT334 is a quad, short-haul, PCM transceiver for 2.048 MHz or 1.544 MHz transmission
systems. Its low impedance transmit output drivers provide constant line impedance whether
transmitting marks or spaces. The output pulse amplitudes are also constant, stabilized against
supply voltage variations.
The LXT334 can be configured for balanced 100/120 Ω or unbalanced 75 Ω systems and
exceeds the latest ETSI return loss recommendations. An on-chip pulse shaping circuit generates
accurate transmit pulses independent of the transmit clock duty cycle. All transmitters and
receivers incorporate a power down mode with output tri-stating.
The LXT334 features differential receiver architecture with high noise interference margin. It
uses peak detection with a variable threshold for reliable recovery of data as low as 500 mV (up
to 12 dB of cable attenuation).
The fully digital clock recovery system uses a low frequency master clock of 2.048 MHz or
1.544 MHz as its reference. Each receiver incorporates a combination analog/digital Loss Of
Signal (LOS) processor that meets the latest ITU G.775 standard. The LXT334 features a driver
failure monitoring circuit in parallel to TTIP and TRING that reports driver shorts.
Applications
s High density line cards using digital
backend ASICs
Product Features
s Fully integrated quad, short-haul PCM
transceiver for G.703 2.048 Mbps or 1.544
Mbps operation
s Single rail supply voltage of 5 V (typical)
s Low power consumption of 410 mW
(typical)
s Programmable G.703 transmit pulse
shaping for G.703 75 Ω, 100 Ω and 120 Ω
systems
s High performance line drivers with
constant low impedance for 20 dB return
loss (typical)
exceeds ETSI 300 166
s On-chip band gap voltage reference for
stabilized, constant output amplitude
s High-performance receivers recover data
with up to 12 dB cable attenuation
s Low frequency 1.544 or 2.048 MHz
reference clock
s On-chip clock recovery function
s Programmable unipolar and bipolar PCM
interface
s On-chip AMI and HDB3 encoder/decoder
s On-chip Driver Failure Monitoring circuit
s Local and remote loopback testing function
s Independent Loss of Signal processor for
each channel conforms to ITU G.775
recommendation
s Small-footprint 64-pin QFP
As of January 15, 2001, this document replaces the Level One document
LXT334 — Quad Short-Haul Transceiver with Clock Recovery.
www.DataSheet4U.com
Order Number: 249077-001
January 2001
1 page  
Quad Short-Haul Transceiver with Clock Recovery — LXT334
Figure 1. LXT334 Block Diagram
Datasheet
5
5 Page 
Quad Short-Haul Transceiver with Clock Recovery — LXT334
2.0
2.1
2.1.1
2.1.1.1
Functional Description
The LXT334 is a fully integrated, quad line interface unit (QLIU) with four complete, independent
transceivers. It supports G.703 applications at both 2.048 Mbps and 1.544 Mbps. All transceivers
operate at the same frequency, determined by the MCLK input. Refer to the LXT334 block
diagram on page 1.
The front end of each transceiver interfaces with four lines, one pair for transmit, and one pair for
receive. Each transmit/receive line set constitutes a digital data loop for full duplex transmission.
Each transceiver also interfaces with back-end processors through bipolar or unipolar data I/O
channels, and allows control by hardwired pins for stand-alone operation.
Receiver
The four receivers in the LXT334 are identical. The following paragraphs describe the operation of
a single receiver.
The LXT334 receives the input signal at RTIP/RRING via a 1:1 transformer.
Data slicers and a peak detector process the received signal. The peak detector samples the
received signal and determines its maximum value. A data-rate dependent percentage of peak value
goes to the data slicers as a threshold level to ensure an optimum signal-to-noise ratio.
The receiver accurately recovers signals with up to -12 dB of cable loss. The minimum receiver
sensitivity signal level is approximately 500 mV. Regardless of the received signal level, the
LXT334 holds its peak detectors above a minimum level (0.225 V) to provide immunity from
impulse noise.
After the data slicers process the received signal, it is fed to the data and timing recovery section,
and to the receive monitor. The data and timing recovery circuits provide an input jitter tolerance
significantly better than required by G.823 as shown in the Test Specifications section.
The recovered clock is output at RCLK in both bipolar and unipolar modes.
In bipolar mode, recovered data is active High and output at RPOS and RNEG; in unipolar mode
recovered data is active High and output at RDATA.
If CNTL2 is Low, RPOS and RNEG outputs are valid on the falling edge of RCLK. IF CNTL1 is
Low and CNTL2 is High, RPOS and RNEG outputs are valid on the rising edge of RCLK.
Asserting MCLK High disables the clock recovery function and switches all receivers to data
recovery mode. In data recovery mode the RPOS/RNEG outputs are active Low. Asserting MCLK
Low powers all receivers down and holds RPOS/RNEG and RCLK in a high impedance state.
Loss Of Signal Detector
LOS Detection at 2.048 MHz
During 2.048 MHz operation, the Loss of Signal (LOS) detector uses a combination analog and
digital detection scheme and complies with the ITU G.775 recommendation.
Datasheet
11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet LXT334.PDF ] | |
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