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STE100P 데이터시트 PDF




ST Microelectronics에서 제조한 전자 부품 STE100P은 전자 산업 및 응용 분야에서
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부품번호 STE100P 기능
기능 10/100 FAST ETHERNET 3.3V TRANSCEIVER
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STE100P 데이터시트, 핀배열, 회로
STE100P
10/100 FAST ETHERNET 3.3V TRANSCEIVER
1 DESCRIPTION
The STE100P, also referred to as STEPHY1, is a
high performance Fast Ethernet physical layer inter-
face for 10Base-T and 100Base-TX applications.
It was designed with advanced CMOS technology to
provide a Media Independent Interface (MII) for easy
attachment to 10/100 Media Access Controllers
(MAC) and a physical media interface for 100Base-
TX of IEEE802.3u and 10Base-T of IEEE802.3.
The STEPHY1 supports both half-duplex and full-du-
plex operation, at 10 and 100 Mbps operation. Its op-
erating mode can be set using auto-negotiation,
parallel detection or manual control. It also allows for
the support of auto-negotiation functions for speed
and duplex detection.
2 FEATURES
2.1 Industry standard
IEEE802.3u 100Base-TX and IEEE802.3
10Base-T compliant
Figure 2. Block Diagram
Figure 1. Package
TQFP64 (10x10x1.40mm)
Table 1. Order Codes
Part Number
STE100P
Package
TQFP64
Support for IEEE802.3x flow control
IEEE802.3u Auto-Negotiation support for
10Base-T and 100Base-TX
MII interface
Standard CSMA/CD or full duplex operation
supported
Industrial temperature compliant
LEDS
LEDS
TX_CLK
TXD[3:0]
TX_ER
TX_EN
MDC
MDIO
100Mb/s
4B/5B
TX Channel
Scrambler
Parallel to
Serial
NRZ To NRZI
Encoder
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Generator
REGISTERS
Auto
Negotiation
Binary To MLT3
Encoder
10 TX
Filter
Loopback
TRANSMITTER
10/100
TXP
TXN
Clock
Generation
System
Clock
RXD[3:0]
RX_ER
RX_DV
RX_CLK
HW
configuration
pins
HW Config
Power Down
100Mb/s
Descrambler
4B/5B Code Align
RX Channel
Serial to
Parallel
NRZI To NRZ
Decoder
Binary To MLT3
Decoder
Clock Recovery
Adaptive
Equalization
BaseLine
Wander
10Mb/s
NRZ To Manchester
Encoder
Link Pulse
Detector
10 TX Filter
Clock Recovery
SMART
Squelch
RECEIVER
10/100
RXP
RXN
September 2004
Rev. 18
1/31




STE100P pdf, 반도체, 판매, 대치품
STE100P
Table 2. Pin Description (continued)
Pin No. Name
Type
Description
52 tx_er
I Transmit Coding Error. The MAC asserts this input when an error has occurred
in the transmit data stream. When the STE100P is operating at 100 Mbps, the
STE100P responds by sending invalid code symbols on the line. In Symbol (5B)
Mode this pin functions as txd4.
51 rxd4
43 rxd3
44 rxd2
46 rxd1
47 rxd0
O Receive Data. The STE100P drives received data on these outputs,
synchronous to rx_clk.
rxd4 is driven only in Symbol (5B) Mode.
48 rx_dv
O Receive Data Valid. The STE100P asserts This signal when it drives valid data
on rxd. This output is synchronous to rx_clk.
51 rx_er
O Receive Error. The STE100P asserts this output when it receives invalid
symbols from the network. This signal is synchronous to rx_clk. In Symbol (5B)
Mode this pin functions as rxd4.
49 rx_clk
O Receive Clock. This continuous clock provides reference for rxd, rx_dv, and
rx_er signals. Refer to the Clock Requirements discussion in the Functional
Description section.
25 MHz for 100 Mbps operation.
2.5 MHz for 10 Mbps operation.
59 col
O Collision Detected. The STE100P asserts this output when detecting a collision.
This output remains High for the duration of the collision. This signal is
asynchronous and inactive during full-duplex operation.
60 crs
O Carrier Sense. During half-duplex operation (PR0:8=0), the STE100P asserts
this output when either transmit or receive medium is non idle. During full duplex
operation (PR0:8=1), crs is asserted only when the receive medium is non-idle.
MII Control Interface
42 mdc
I Management Data Clock. Clock for the mdio serial data channel. Maximum
frequency is 2.5 MHz.
41 mdio
I/O Management Data Input/Output, Bi-directional serial data channel for PHY
communication.
61 mdint OD Management Data Interrupt. When any bit in PR18 = 1, an active High output
on this pin indicates status change in the corresponding bits in PR17.
Interrupt is cleared by reading Register PR17. Requires MDC edge to output.
Physical (Twisted Pair) Interface
12 x1
I 25 MHz reference clock input. When an external 25 MHz crystal is used, this pin
will be connected to one terminal of it. If an external 25 MHz clock source of
oscillator is used, then this pin will be the input pin of it.
11 x2
O 25 MHz reference clock output. When an external 25MHz crystal is used, this pin
will be connected to another terminal of if. If an external clock source is used,
then this pin should be left open.
21 txp
23 txn
O The differential Transmit outputs of 100Base-TX or 10Base-T, these pins directly
output to the transformer.
19 rxp
18 rxn
I The differential Receive inputs of 100Base-TX or 10Base-T, these pins directly
input from the transformer.
4/31

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STE100P 전자부품, 판매, 대치품
STE100P
5 HARDWARE CONTROL INTERFACE
5.1 Operating Configurations
The Hardware Control Interface consists of the MF<4:0>, CFG <1:0> and FDE input pins as well as the LED/
PAD pins. This interface is used to configure operating characteristics of the STE100P. The Hardware Control
Interface provides initial values for the MDIO registers, and then passes control to the MDIO Interface. Individual
chip addressing via the LED/PAD pins allows multiple STE100P devices to share the MII interface. Table 3
shows how to set up the desired operating configurations using the Hardware Control Interface.
Table 3. Operating Configurations / Auto-Negotiation Enabled
Desired
Configuration
Input Value
CFG0 CFG1
FDE
PR4 Register Bits Affected
[8] TXF [7] TXH [6] 10F [5] 10H
Advertise All
111
1
1
1
1
Advertise 100 HD
100
0
1
0
0
Advertise 100 HD/FD
101
1
1
0
0
Advertise 10 HD
010
0
0
0
1
Advertise 10 HD/FD
011
0
0
1
1
Advertise 10/100 HD
110
0
1
0
1
Note: If pin 5, MF0 = 0, or ANE (pin MF0 / PR0:12) = 0 (Auto-Negotiation disabled), then PR4 bits 5-8 will contain the default value indicated
in the table describing register PR4.
5.2 LED / PHY Address Interface
The LED output pins can be used to drive LED’s directly, or can be used to provide status information to a net-
work management device. The active state of each LED output driver is dependent on the logic level sampled
by the corresponding PHY address input upon power-up/reset. For example, if a given PAD input is resistively
pulled low then the corresponding LED output will be configured as an active high driver. Conversely, if a given
PAD input is resistively pulled high then the corresponding LED output will be configured as an active low driver.
These outputs are standard CMOS drivers and not open-drain.
The STE100P PAD[4:0] inputs provide up to 32 unique PHY address options. An address selection of all zeros
(00000) will result in a PHY isolation condition as a result of power-on/reset, as documented for PR0 bit 10.
(See Section 7 for more detailed descriptions of device operation.)
7/31

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