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SH66P20A 데이터시트 PDF




Sino Wealth Microelectronic에서 제조한 전자 부품 SH66P20A은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 SH66P20A 기능
기능 OTP 4-Bit Microcontroller
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SH66P20A 데이터시트, 핀배열, 회로
SH66P20A
OTP 4-bit Microcontroller
Features
SH6610C-based single-chip 4-bit microcontroller
ROM: 1K X 16 bits
RAM: 64 X 4 bits (Data memory)
Operation voltage: 2.4V - 6.0V (Typical 3.0V or 5.0V)
12 CMOS bi-directional I/O pins
4-level subroutine nesting (including interrupts)
One 8-bit auto re-load timer/counter
Warm-up timer for power on reset
Powerful interrupt sources:
- Internal interrupt (Timer0)
- External interrupts: PortB & PortC (Falling edge)
Oscillator (user option)
- X`tal oscillator:
32.768KHz ~ 4MHz
- Ceramic resonator: 400K ~ 4MHz
- RC oscillator:
400K ~ 4MHz
- External clock:30K ~ 4MHz
Instruction cycle time:
- 4/32.768KHz (122us) for 32.768KHz OSC clock
- 4/4MHz (= 1us) for 4MHz OSC clock
Two low power operation modes: HALT and STOP
OTP type
Code protection
Built-in watchdog timer
General Description
SH66P20A is a 4-bit microcontroller. This chip integrates the SH6610C 4-bit CPU core with SRAM, 1K program ROM, Timer
and I/O Port.
Pin Configuration
PORTA.2
PORTA.3
T0
RESET
GND
PORTB.0
PORTB.1
PORTB.2
PORTB.3
1
2
3
4
5
6
7
8
9
18 PORTA.1
17 PORTA.0
16 OSCI
15 OSCO
14 VDD
13 PORTC.3
12 PORTC.2
11 PORTC.1
10 PORTC.0
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SH66P20A pdf, 반도체, 판매, 대치품
SH66P20A
3. RAM
Built-in RAM consists of general-purpose data memory and system register. Direct addressing in one instruction can
accessed data memory and system register.
The following is the memory allocation map:
$000 - $01F: System register and I/O.
$020 - $05F: Data memory (64 X 4 bits).
The Configuration of System Register
Address
Bit3
Bit2
Bit1
Bit0 R/W
Remarks
$00
- IET0 -
IEP R/W Interrupt enable flags
$01
- IRQT0 -
IRQP R/W Interrupt request flags
$02
-
TM0.2
TM0.1
TM0.0 R/W Timer0 Mode register (Prescaler)
$03 - - - - - Reserved
$04
T0L.3
T0L.2
T0L.1
T0L.0 R/W Timer0 load/counter register low digit
$05
T0H.3
T0H.2
T0H.1
T0H.0 R/W Timer0 load/counter register high digit
$06 - - - - - Reserved
$07
LPD3
LPD2
LPD1
LPD0
W LPD Control (0AH: Enable, 05H: Disable)
$08
PA.3
PA.2
PA.1
PA.0
R/W PORTA
$09
PB.3
PB.2
PB.1
PB.0
R/W PORTB
$0A
PC.3
PC.2
PC.1
PC.0
R/W PORTC
$0B - $0D
$0E
-
TBR.3
-
TBR.2
-
TBR.1
-
TBR.0
- Reserved
R/W Table Branch Register
$0F
INX.3
INX.2
INX.1
INX.0 R/W Pseudo index register
$10
DPL.3
DPL.2
DPL.1
DPL.0 R/W Data pointer for INX low nibble
$11 - DPM.0 DPM.1 DPM.0 R/W Data pointer for INX middle nibble
$12 - - - - - Reserved
$13 - $15
-
-
-
- - Reserved
$16 PA3OUT PA2OUT PA1OUT PA0OUT W Set PORTA to be output port
$17 PB3OUT PB2OUT PB1OUT PB0OUT W Set PORTB to be output port
$18 PC3OUT PC2OUT PC1OUT PC0OUT W Set PORTC to be output port
$19 - $1B
$1C
-
-
- - - - Reserved.
- T0S T0E W Bit0: T0 signal edge, Bit1: T0 signal source
$1D - - - - - Reserved
$1E WDT
-
-
- W Bit3: WDT time-out bit (write one only)
$1F - - - - - Reserved
* System Register $00 - $12 (Please refer to "SH6610C User’s manual").
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SH66P20A 전자부품, 판매, 대치품
SH66P20A
PORTB & PORTC interrupt
The PORTB and PORTC are used as port interrupt sources. Since PORT I/O is bit programmable I/O, so only the input port can
generate an external interrupt. Any one of the PORTB and PORTC input pin transitions from VDD to GND will generate an
interrupt request. And further falling edge transition would not be able to make interrupt request until all of the pins return to VDD.
Following is the port interrupt function block-diagram.
PORTC.3
PC3OUT
PORTC.2
PC2OUT
PORTC.1
PC1OUT
PORTC.0
PC0OUT
PORTB.3
PB3OUT
PORTB.2
PB2OUT
PORTB.1
PB1OUT
PORTB.0
PB0OUT
FALLING EDGE
DETECTION
PORT
INTERRUPT
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SH66P20A

OTP 4-Bit Microcontroller

Sino Wealth Microelectronic
Sino Wealth Microelectronic

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