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부품번호 S71PL127 기능
기능 (S71PLxxx) STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM
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S71PL127 데이터시트, 핀배열, 회로
S71PL254/127/064/032J based MCPs
Stacked Multi-Chip Product (MCP) Flash Memory and RAM
256M/128/64/32 Megabit (16/8/4/2M x 16-bit) CMOS 3.0 Volt-only
Simultaneous Operation Page Mode Flash Memory and
64/32/16/8/4 Megabit (4M/2M/1M/512K/256K x 16-bit) Static
RAM/Pseudo Static RAM
Datasheet
ADVANCE
Distinctive Characteristics
MCP Features
„ Power supply voltage of 2.7 to 3.1 volt
„ High performance
— 55 ns
— 65 ns (65 ns Flash, 70ns pSRAM)
„ Packages
— 7 x 9 x 1.2mm 56 ball FBGA
— 8 x 11.6 x 1.2mm 64 ball FBGA
— 8 x 11.6 x 1.4mm 84 ball FBGA
„ Operating Temperature
— –25°C to +85°C
— –40°C to +85°C
General Description
The S71PL series is a product line of stacked Multi-Chip Product (MCP) packages
and consists of:
„ One or more S29PL (Simultaneous Read/Write) Flash memory die
„ pSRAM or SRAM
The 256Mb Flash memory consists of two S29PL127J devices. In this case, CE#f2
is used to access the second Flash and no extra address lines are required.
The products covered by this document are listed in the table below:
pSRAM
Density
4Mb
8Mb
16Mb
32Mb
64Mb
32Mb
S71PL032J40
S71PL032J80
S71PL032JA0
Flash Memory Density
64Mb
128Mb
S71PL064J80
S71PL064JA0
S71PL064JB0
S71PL127JA0
S71PL127JB0
S71PL127JC0
256Mb
S71PL254JB0
S71PL254JC0
SRAM Density (Note)
Flash Memory Density
32Mb
64Mb
4Mb S71PL032J04
8Mb
S71PL032J08
S71PL064J08
Note: Not recommended for new designs; use pSRAM based MCPs instead.
www.DataSheet4U.com
Publication Number S71PL254/127/064/032J_00 Revision A Amendment 6 Issue Date November 22, 2004
www.DataSheet4U.com




S71PL127 pdf, 반도체, 판매, 대치품
Advance Information
S71PL254/127/064/032J based MCPs
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . 1
MCP Features ........................................................................................................ 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
32Mb Flash Memory .............................................................................................2
64Mb Flash Memory .............................................................................................2
128Mb Flash Memory ...........................................................................................3
256Mb Flash Memory (2xS29PL127J) ...............................................................3
Connection Diagram (S71PL032J) . . . . . . . . . . . . . .9
Connection Diagram (S71PL064J) . . . . . . . . . . . . . 10
Connection Diagram (S71PL127J) . . . . . . . . . . . . . 11
Connection Diagram (S71PL254J) . . . . . . . . . . . . . 12
Special Handling Instructions For FBGA Package ................................. 12
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 14
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . .20
TLC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7mm Package ................................................................................................ 20
TSC056—56-ball Fine-Pitch Ball Grid Array (FBGA)
9 x 7mm Package ................................................................................................. 21
TLA064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6mm Package ............................................................................................ 22
TSB064—64-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6 mm Package ...........................................................................................23
FTA084—84-ball Fine-Pitch Ball Grid Array (FBGA)
8 x 11.6mm ............................................................................................................ 24
S29PL127J/S29PL064J/S29PL032J for MCP
General Description . . . . . . . . . . . . . . . . . . . . . . . 27
Simultaneous Read/Write Operation with Zero Latency ......................27
Page Mode Features ...........................................................................................27
Standard Flash Memory Features ...................................................................27
Product Selector Guide . . . . . . . . . . . . . . . . . . . . .29
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Simultaneous Read/Write Block Diagram . . . . . . 31
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . 33
Table 1. PL127J Device Bus Operations ................................ 33
Requirements for Reading Array Data .........................................................33
Random Read (Non-Page Read) ................................................................33
Page Mode Read ..............................................................................................34
Table 2. Page Select .......................................................... 34
Simultaneous Read/Write Operation ...........................................................34
Table 3. Bank Select .......................................................... 34
Writing Commands/Command Sequences .................................................35
Accelerated Program Operation ...............................................................35
Autoselect Functions .....................................................................................35
Standby Mode .......................................................................................................35
Automatic Sleep Mode ......................................................................................36
RESET#: Hardware Reset Pin .........................................................................36
Table 4. PL127J Sector Architecture ..................................... 37
Table 5. PL064J Sector Architecture ..................................... 44
Table 6. PL032J Sector Architecture ..................................... 47
Table 7. Secured Silicon Sector Addresses ............................ 48
Autoselect Mode ................................................................................................ 49
4
Table 8. Autoselect Codes (High Voltage Method) .................. 49
Table 9. PL127J Boot Sector/Sector Block Addresses for Protection/
Unprotection ..................................................................... 50
Table 10. PL064J Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................... 51
Table 11. PL032J Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................... 52
Selecting a Sector Protection Mode ............................................................. 52
Table 12. Sector Protection Schemes ................................... 53
Sector Protection . . . . . . . . . . . . . . . . . . . . . . . . . 53
Sector Protection Schemes . . . . . . . . . . . . . . . . . 53
Password Sector Protection ........................................................................... 53
WP# Hardware Protection ............................................................................. 53
Selecting a Sector Protection Mode ............................................................. 53
Persistent Sector Protection . . . . . . . . . . . . . . . . 54
Persistent Protection Bit (PPB) ...................................................................... 54
Persistent Protection Bit Lock (PPB Lock) ................................................. 54
Persistent Sector Protection Mode Locking Bit ....................................... 56
Password Protection Mode . . . . . . . . . . . . . . . . . 56
Password and Password Mode Locking Bit ................................................ 56
64-bit Password .................................................................................................. 57
Write Protect (WP#) ....................................................................................... 57
Persistent Protection Bit Lock ................................................................... 57
High Voltage Sector Protection .....................................................................58
Figure 1. In-System Sector Protection/Sector Unprotection
Algorithms........................................................................ 59
Temporary Sector Unprotect ........................................................................60
Figure 2. Temporary Sector Unprotect Operation ................... 60
Secured Silicon Sector Flash Memory Region ...........................................60
Factory-Locked Area (64 words) ...............................................................61
Customer-Lockable Area (64 words) .......................................................61
Secured Silicon Sector Protection Bits .....................................................61
Figure 3. Secured Silicon Sector Protect Verify ...................... 62
Hardware Data Protection .............................................................................62
Low VCC Write Inhibit ................................................................................62
Write Pulse “Glitch” Protection ...............................................................62
Logical Inhibit ...................................................................................................62
Power-Up Write Inhibit ...............................................................................62
Common Flash Memory Interface (CFI) . . . . . . 63
Table 13. CFI Query Identification String .............................. 63
Table 14. System Interface String ........................................ 64
Table 15. Device Geometry Definition ................................... 64
Table 16. Primary Vendor-Specific Extended Query ................ 65
Command Definitions . . . . . . . . . . . . . . . . . . . . . 66
Reading Array Data ...........................................................................................66
Reset Command .................................................................................................66
Autoselect Command Sequence .................................................................... 67
Enter Secured Silicon Sector/Exit Secured Silicon Sector Command Se-
quence .................................................................................................................... 67
Word Program Command Sequence ........................................................... 67
Unlock Bypass Command Sequence ........................................................68
Figure 4. Program Operation ............................................... 69
Chip Erase Command Sequence ...................................................................69
Sector Erase Command Sequence ................................................................70
Figure 5. Erase Operation ................................................... 71
Erase Suspend/Erase Resume Commands ................................................... 71
Command Definitions Tables ......................................................................... 72
Table 17. Memory Array Command Definitions ...................... 72
Table 18. Sector Protection Command Definitions .................. 73
Write Operation Status . . . . . . . . . . . . . . . . . . . . 74
DQ7: Data# Polling ............................................................................................ 75
S71PL254/127/064/032J_00_A6 November 22, 2004

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S71PL127 전자부품, 판매, 대치품
Advance Information
is Low, Ignore UB#/LB# Timing) ........................................ 161
Figure 82. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 161
Figure 83. Timing Waveform of Write Cycle(2) (CS# controlled, if
BYTE# is Low, Ignore UB#/LB# Timing).............................. 162
Figure 84. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled) ...................................................................... 162
Figure 85. Data Retention Waveform .................................. 163
pSRAM Type 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Functional Description . . . . . . . . . . . . . . . . . . . . 164
Absolute Maximum Ratings . . . . . . . . . . . . . . . . 164
Timing Test Conditions . . . . . . . . . . . . . . . . . . . 170
Output Load Circuit ......................................................................................... 171
Figure 86. Output Load Circuit ........................................... 171
Power Up Sequence . . . . . . . . . . . . . . . . . . . . . . . 171
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 183
Read Cycle .......................................................................................................... 183
Figure 87. Timing of Read Cycle (CE# = OE# = VIL, WE# = ZZ# =
VIH)................................................................................ 183
Figure 88. Timing Waveform of Read
Cycle (WE# = ZZ# = VIH) ................................................ 184
Figure 89. Timing Waveform of Page Mode Read Cycle (WE# = ZZ#
= VIH)............................................................................ 185
Write Cycle .........................................................................................................186
Figure 90. Timing Waveform of Write Cycle (WE# Control, ZZ# =
VIH) ............................................................................... 186
Figure 91. Timing Waveform of Write Cycle (CE# Control, ZZ# =
VIH) ............................................................................... 186
Figure 92. Timing Waveform of Page Mode Write Cycle (ZZ# = VIH)
187
Partial Array Self Refresh (PAR) .................................................................. 188
Temperature Compensated Refresh (for 64Mb) ................................... 188
Deep Sleep Mode ............................................................................................. 188
Reduced Memory Size (for 32M and 16M) ................................................ 188
Other Mode Register Settings (for 64M) ...................................................189
Figure 93. Mode Register .................................................. 189
Figure 94. Mode Register Update Timings (UB#, LB#, OE# are
Don’t Care)..................................................................... 190
Figure 95. Deep Sleep Mode - Entry/Exit Timings................. 190
Revision Summary
November 22, 2004 S71PL254/127/064/032J_00_A6
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관련 데이터시트

부품번호상세설명 및 기능제조사
S71PL127

(S71PLxxx) STACKED MULTI CHIP PRODUCT FLASH MEMORY AND RAM

SPANSION
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S71PL127J

Based MCPs

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