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DM74LS95B 데이터시트 PDF




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부품번호 DM74LS95B 기능
기능 4-BIR RIGHT/LEFT SHIFT REGISTER
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DM74LS95B 데이터시트, 핀배열, 회로
www.DataSheet4U.com
April 1992
DM54LS95B DM74LS95B
4-Bit Right Left Shift Register
General Description
The ’LS95B is a 4-bit shift register with serial and parallel
synchronous operating modes The serial shift right and par-
allel load are activated by separate clock inputs which are
selected by a mode control input The data is transferred
from the serial or parallel D inputs to the Q outputs synchro-
nous with the HIGH-to-LOW transition of the appropriate
clock input
Features
Y Synchronous expandable shift right
Y Synchronous shift left capability
Y Synchronous parallel load
Y Separate shift and load clock inputs
Connection Diagram
Logic Symbol
Dual-In-Line Package
TL F 10175– 1
Order Number DM54LS95BJ DM54LS95BN
DM74LS95BM or DM74LS95BN
See NS Package Number J14A M14A N14A or W14B
VCC e Pin 14
GND e Pin 7
Pin Names
CP1
CP2
DS
P0– P3
PE
Q0– Q3
Description
Serial Clock Input (Active Falling Edge)
Parallel Clock Input (Active Falling Edge)
Serial Data Input
Parallel Data Inputs
Parallel Enable Input (Active HIGH)
Parallel Outputs
TL F 10175– 2
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C1995 National Semiconductor Corporation TL F 10175
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RRD-B30M105 Printed in U S A
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DM74LS95B pdf, 반도체, 판매, 대치품
Functional Description
The ’95 is a 4-bit shift register with serial and parallel syn-
chronous operating modes It has a Serial (DS) and four
Parallel (P0 – P3) Data inputs and four Parallel Data outputs
(Q0 – Q3) The serial or parallel mode of operation is con-
trolled by a Parallel Enable input (PE) and two Clock inputs
CP1 and CP2 The serial (right-shift) or parallel data trans-
fers occur synchronous with the HIGH-to-LOW transition of
the selected clock input
When PE is HIGH CP2 is enabled A HIGH-to-LOW tran-
sition on enabled CP2 transfers parallel data from the P0–
P3 inputs to the Q0–Q3 outputs When PE is LOW CP1 is
enabled A HIGH-to-LOW transition on enabled CP1 trans-
fers the data from Serial input (DS) to Q0 and shifts the data
in Q0 to Q1 Q1 to Q2 and Q2 to Q3 respectively (right-
shift) A left-shift is accomplished by externally connecting
Q3 to P2 Q2 to P1 and Q1 to P0 and operating the ’95 in
the parallel mode (PE e HIGH) For normal operation PE
should only change states when both Clock inputs are
LOW However changing PE from LOW to HIGH while CP2
is HIGH or changing PE from HIGH to LOW while CP1 is
HIGH and CP2 is LOW will not cause any changes on the
register outputs
Mode Select Table
Operating
Mode
Shift
Inputs
Outputs
PE CP1 CP2 DS Pn Q0 Q1 Q2 Q3
LKX
LKX
I X L q0 q1 q2
h X H q0 q1 q2
Parallel Load H
X K X pn p0 p1 p2 p3
Mode Change
K
L
K
L
K
L
K
L
L
L
H
H
L
L
H
H
L X X No Change
L X X No Change
L X X No Change
X X Undetermined
H X X Undetermined
H X X No Change
H X X Undetermined
H X X No Change
I e LOW Voltage Level one set-up time prior to the HIGH-to-LOW clock transition
h e HIGH Voltage Level one set-up time prior to the HIGH-to-LOW clock transition
pn e Lower case letters indicate the state of the referenced input (or output) one set-up time prior to
the HIGH-to-LOW clock transition
H e HIGH Voltage Level
L e LOW Voltage Level
X e Immaterial
FIGURE A
TL F 10175 – 3
4

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DM74LS95B 전자부품, 판매, 대치품
Physical Dimensions inches (millimeters) (Continued)
14-Lead Small Outline Molded Package (M)
Order Number DM74LS95BM
NS Package Number M14A
14-Lead Molded Dual-In-Line Package (N)
Order Number DM74LS95BN
NS Package Number N14A
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