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PDF IT8661F Data sheet ( Hoja de datos )

Número de pieza IT8661F
Descripción Plug and Play Super AT I/O
Fabricantes Integrated Technology Express　
Logotipo Integrated Technology Express Logotipo



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IT8661F
Plug and Play Super AT I/O
Preliminary Specification V0.6
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IT8661F pdf
6.11.12 IR DMA Channel Select 2 (Index=75h, Default=00h, ISA PnP/MB PnP).............................. 25
6.11.13 IR Special Configuration Register (Index=F0h, Default=00h, MB PnP)................................ 26
6.12 GPIO & Alternate Function Configuration Registers (LDN=05h)..................................................... 26
6.12.1 CS0 Base Address MSB Register (Index=60h, Default=00h, MB PnP).................................... 26
6.12.2 CS0 Base Address LSB Register (Index=61h, Default=00h, MB PnP)..................................... 26
6.12.3 CS1 Base Address MSB Register (Index=62h, Default=00h, MB PnP).................................... 26
6.12.4 CS1 Base Address LSB Register (Index=63h, Default=00h, MB PnP)..................................... 26
6.12.5 CS2 Base Address MSB Register (Index=64h, Default=00h, MB PnP).................................... 26
6.12.6 CS2 Base Address LSB Register (Index=65h, Default=00h, MB PnP)..................................... 26
6.12.7 Simple I/O Base Address MSB Register (Index=66h, Default=00h, MB PnP).......................... 27
6.12.8 Simple I/O Base Address LSB Register (Index=67h, Default=00h, MB PnP)........................... 27
6.12.9 GPIO Interrupt Level Select (Index=70h, Default=00h, MB PnP) ............................................ 27
6.12.10 GPIO[7:0] Pin Polarity Register (Index=F0h, Default=00h, MB PnP) ................................... 27
6.12.11 CS0/CS1/CS2 Control Register (Index=F1h/F2h/F3h, Default=00h, MB PnP) ..................... 27
6.12.12 GPIO[7:0] Function Selection Register (Index=F4h, Default=00h, MB PnP) ........................ 27
6.12.13 Simple I/O[7:0] Direction Selection Register (Index=F5h, Default=00h, MB PnP) ................ 27
6.12.14 Zero Wait State Control & On-Chip High Address Qualification Enable Register (Index=F6h,
Default=00h, MB PnP).......................................................................................................................... 28
6.12.15 Device Zero Wait State Enable Register (Index=F7h, Default=00h, MB PnP) ..................... 28
6.12.16 GPIO[12:8] Pin Polarity Register (Index=F8h, Default=00h, MB PnP) ................................. 28
6.12.17 GPIO[12:8] Function Selection Register (Index=F9h, Default=00h, MB PnP) ...................... 28
6.12.18 Simple I/O[12:8] Direction Selection Register (Index=FAh, Default=00h, MB PnP).............. 28
6.12.19High Address Qualification Inputs 1 & 2 Selection Register (Index=FBh, Default = 00h, MB PnP)29
6.12.20High Address Qualification Inputs 3 & 4 Selection Register (Index=FCh, Default = 00h, MB PnP)29
7. Functional Description....................................................................................................................... 30
7.1 General Purpose I/O...................................................................................................................... 30
7.2 FDC Register Description .............................................................................................................. 32
7.2.1 Digital Output Register (DOR) - (Base Address + 02h)............................................................ 32
7.2.2 Main Status Register (MSR) - (Base Address + 04h)............................................................... 32
7.2.3 Data Register (FIFO) - (Base Address + 05h).......................................................................... 33
7.2.4 Digital Input Register (DIR) - (Base + 07h) .............................................................................. 33
7.2.5 Diskette Control Register (DCR) - (Base Address + 07h WRITE) ............................................ 33
7.2.6 Status Register ....................................................................................................................... 34
7.2.7 Reset ...................................................................................................................................... 36
7.2.8 Controller Phases ................................................................................................................... 36
7.2.9 Data Transfer Commands Description .................................................................................... 36
7.3 Serial Channel Register Description............................................................................................... 49
7.3.1 Data Register.......................................................................................................................... 49
7.3.2 Control Registers: IER, IIR, FCR, DLL, DLM, LCR, MCR ........................................................ 49
7.3.3 Status Register LSR and MSR ................................................................................................ 51
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IT8661F arduino
2. General Description
The IT8661F Plug and Play Super AT I/O chip
is a user-friendly, low cost peripheral
controller. It provides an ideal solution for
Microsoft PC97/98 (PC99 ready) system
requirements. A programmable IRQ sharing
function is supported to comply with Microsoft
PC97/98 (PC99 ready) requirements. No N.V.
memory is needed to store resource data for
Plug and Play system applications.
The IT8661F consists of five logical devices.
One high performance 2.88MB floppy disk
controller, with digital data separator, supports
two 360K/ 720K/ 1.2M/ 1.44M/ 2.88M floppy
disk drives. One multi-mode high
performance Parallel Port features the bi-
directional Standard Parallel Port (SPP), the
Enhanced Parallel Port (EPP. V1.7 and v1.9
are supported), and IEEE 1284 compliant
Extended Capabilities Port (ECP). Two
16C550 standard compatible enhanced
IT8661F
UARTs perform asynchronous communication
for serial ports. One highly integrated infrared
communication controller is capable of
supporting HPSIR, MIR, or ASKIR with a built-
in dedicated 16C550 standard compatible
UART.
These five logical devices can be individually
enabled or disabled via software configuration
registers. The IT8661F utilizes power saving
circuitry to reduce power consumption. Once
a logical device is disabled, its related inputs
are gate inhibited, outputs are tristated, and
input clock is disabled. The Parallel Port
includes a specifically designed circuit to
reduce damage or backdrive current when a
printer or another parallel port device is
powered-on. In effect, the IT8661F is a high-
performance, low-power consumption I/O
device.
2

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