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28F320J3A 데이터시트 PDF




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부품번호 28F320J3A 기능
기능 (28FxxxJ3A) Intel StrataFlash Memory
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28F320J3A 데이터시트, 핀배열, 회로
3 Volt Intel® StrataFlashMemory
28F128J3A, 28F640J3A, 28F320J3A (x8/x16)
Preliminary Datasheet
Product Features
s High-Density Symmetrically-Blocked
Architecture
128 128-Kbyte Erase Blocks (128 M)
64 128-Kbyte Erase Blocks (64 M)
32 128-Kbyte Erase Blocks (32 M)
s High Performance Interface Asynchronous
Page Mode Reads
110/25 ns Read Access Time (32 M)
120/25 ns Read Access Time (64 M)
150/25 ns Read Access Time (128 M)
s 2.7 V3.6 V VCC Operation
s 128-bit Protection Register
64-bit Unique Device Identifier
64-bit User Programmable OTP Cells
s Enhanced Data Protection Features
Absolute Protection with VPEN = GND
Flexible Block Locking
Block Erase/Program Lockout during
Power Transitions
s Packaging
56-Lead TSOP Package
64-Ball Intel® Easy BGA Package
s Cross-Compatible Command Support Intel
Basic Command Set
Common Flash Interface
Scalable Command Set
s 32-Byte Write Buffer
6 µs per Byte Effective Programming
Time
s 12.8M Total Min. Erase Cycles (128 Mbit)
6.4M Total Min. Erase Cycles (64 Mbit)
3.2M Total Min. Erase Cycles (32 Mbit)
100K Minimum Erase Cycles per Block
s Automation Suspend Options
Block Erase Suspend to Read
Block Erase Suspend to Program
Program Suspend to Read
s 0.25 µ Intel® StrataFlashMemory
Technology
Capitalizing on Intel’s 0.25 µ generation two-bit-per-cell technology, second generation Intel®
StrataFlashmemory products provide 2X the bits in 1X the space, with new features for mainstream
performance. Offered in 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, these devices bring
reliable, two-bit-per-cell storage technology to the flash market segment.
Benefits include: more density in less space, high-speed interface, lowest cost-per-bit NOR devices,
support for code and data storage, and easy migration to future devices.
Using the same NOR-based ETOXtechnology as Intels one-bit-per-cell products, Intel StrataFlash
memory devices take advantage of over one billion units of manufacturing experience since 1987. As a
result, Intel StrataFlash components are ideal for code and data applications where high density and low
cost are required. Examples include networking, telecommunications, digital set top boxes, audio
recording, and digital imaging.
By applying FlashFilememory family pinouts, Intel StrataFlash memory components allow easy design
migrations from existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation
Intel StrataFlash memory (28F640J5 and 28F320J5) devices.
Intel StrataFlash memory components deliver a new generation of forward-compatible software support.
By using the Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take
advantage of density upgrades and optimized write capabilities of future Intel StrataFlash memory devices.
Manufactured on Intel® 0.25 micron ETOXVI process technology, Intel StrataFlash memory provides
the highest levels of quality and reliability.
Notice: This document contains preliminary information on new products in production. The
specifications are subject to change without notice. Verify with your local Intel sales office that
you have the latest datasheet before finalizing a design.
Order Number: 290w6w6w7-.0D0a8taSheet4U.com
April 2001
www.DataSheet4U.com
www.DataSheet4U.com




28F320J3A pdf, 반도체, 판매, 대치품
28F128J3A, 28F640J3A, 28F320J3A
Buffers or Transceivers39
5.5 VCC, VPEN, RP# Transitions ............................................................................. 39
5.6 Power-Up/Down Protection................................................................................. 39
5.7 Power Dissipation ............................................................................................... 40
6.0 Electrical Specifications........................................................................................ 40
6.1 Absolute Maximum Ratings ................................................................................ 40
6.2 Operating Conditions .......................................................................................... 41
6.3 Capacitance ........................................................................................................ 41
6.4 DC Characteristics .............................................................................................. 42
6.5 AC CharacteristicsRead-Only Operations(1,2)................................................. 45
6.6 AC CharacteristicsWrite Operations(1,2) ......................................................... 47
6.7 Block Erase, Program, and Lock-Bit Configuration Performance(1,2,3) ............... 48
7.0 Ordering Information .............................................................................................. 51
8.0 Additional Information ........................................................................................... 52
iv Preliminary

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28F320J3A 전자부품, 판매, 대치품
1.0
28F128J3A, 28F640J3A, 28F320J3A
Product Overview
The 0.25 µ 3 Volt Intel StrataFlash memory family contains high-density memories organized as
16 Mbytes or 8 Mwords (128-Mbit), 8 Mbytes or 4 Mwords (64-Mbit), and 4 Mbytes or 2 Mwords
(32-Mbit). These devices can be accessed as 8- or 16-bit words. The 128-Mbit device is organized
as one-hundred-twenty-eight 128-Kbyte (131,072 bytes) erase blocks. The 64-Mbit device is
organized as sixty-four 128-Kbyte erase blocks while the 32-Mbits device contains thirty-two
128-Kbyte erase blocks. Blocks are selectively and individually lockable and unlockable in-
system. A 128-bit protection register has multiple uses, including unique flash device
identification.
The devices optimized architecture and interface dramatically increases read performance by
supporting page-mode reads. This read mode is ideal for non-clock memory systems.
A Common Flash Interface (CFI) permits software algorithms to be used for entire families of
devices. This allows device-independent, JEDEC ID-independent, and forward- and backward-
compatible software support for the specified flash device families. Flash vendors can standardize
their existing interfaces for long-term compatibility.
Scalable Command Set (SCS) allows a single, simple software driver in all host systems to work
with all SCS-compliant flash memory devices, independent of system-level packaging (e.g.,
memory card, SIMM, or direct-to-board placement). Additionally, SCS provides the highest
system/device data transfer rates and minimizes device and system-level implementation costs.
A Command User Interface (CUI) serves as the interface between the system processor and
internal operation of the device. A valid command sequence written to the CUI initiates device
automation. An internal Write State Machine (WSM) automatically executes the algorithms and
timings necessary for block erase, program, and lock-bit configuration operations.
A block erase operation erases one of the devices 128-Kbyte blocks typically within one second
independent of other blocks. Each block can be independently erased 100,000 times. Block erase
suspend mode allows system software to suspend block erase to read or program data from any
other block. Similarly, program suspend allows system software to suspend programming (byte/
word program and write-to-buffer operations) to read data or execute code from any other block
that is not being suspended.
Each device incorporates a Write Buffer of 32 bytes (16 words) to allow optimum programming
performance. By using the Write Buffer, data is programmed in buffer increments. This feature can
improve system program performance more than 20 times over non-Write Buffer writes.
Individual block locking uses block lock-bits to lock and unlock blocks. Block lock-bits gate block
erase and program operations. Lock-bit configuration operations set and clear lock-bits (Set Block
Lock-Bit and Clear Block Lock-Bits commands).
The status register indicates when the WSMs block erase, program, or lock-bit configuration
operation is finished.
The STS (STATUS) output gives an additional indicator of WSM activity by providing both a
hardware signal of status (versus software polling) and status masking (interrupt masking for
background block erase, for example). Status indication using STS minimizes both CPU overhead
and system power consumption. When configured in level mode (default mode), it acts as a RY/
BY# pin. When low, STS indicates that the WSM is performing a block erase, program, or lock-bit
configuration. STS-high indicates that the WSM is ready for a new command, block erase is
Preliminary
1

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관련 데이터시트

부품번호상세설명 및 기능제조사
28F320J3

(28FxxxJ3) Strata Flash Memory

Intel
Intel
28F320J3A

(28FxxxJ3A) Intel StrataFlash Memory

Intel Corporation
Intel Corporation

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