PDF CY7C453 Data sheet ( Hoja de datos )

Número de pieza	CY7C453
Descripción	(CY7C451 - CY7C454) Cascadable Colcked FIFOs
Fabricantes	Cypress Semiconductor
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No Preview Available ! 54 CY7C451 CY7C453 CY7C454 512x9, 2Kx9, and 4Kx9 Cascadable Clocked FIFOs with Programmable Features • High-speed, low-power, first-in first-out (FIFO) memories • 512 x 9 (CY7C451) • 2,048 x 9 (CY7C453) • 4,096 x 9 (CY7C454) • 0.65 micron CMOS for optimum speed/power • High-speed 83-MHz operation (12 ns read/write cycle time) • Low power — ICC=70 mA • Fully asynchronous and simultaneous read and write operation • Empty, Full, Half Full, and programmable Almost Empty and Almost Full status flags • TTL compatible • Retransmit function • Parity generation/checking • Output Enable (OE) pins • Independent read and write enable pins • Center power and ground pins for reduced noise • Supports free-running 50% duty cycle clock inputs • Width Expansion Capability • Depth Expansion Capability • Available in PLCC packages Functional Description The CY7C451, CY7C453, and CY7C454 are high-speed, low-power, first-in first-out (FIFO) memories with clocked read and write interfaces. Both FIFOs are 9 bits wide. The CY7C451 has a 512-word by 9-bit memory array, the CY7C453 has a 2048-word by 9-bit memory array, and the CY7C454 has a 4096-word by 9-bit memory array. Devices can be cascaded to increase FIFO depth. Programmable fea- tures include Almost Full/Empty flags and generation/checking of parity. These FIFOs provide solutions for a wide variety of data buffering needs, including high-speed data acquisition, multiproces- sor interfaces, and communications buffering. Both FIFOs have 9-bit input and output ports that are con- trolled by separate clock and enable signals. The input port is controlled by a free-running clock (CKW) and a write enable pin (ENW). When ENW is asserted, data is written into the FIFO on the rising edge of the CKW signal. While ENW is held active, data is continually written into the FIFO on each CKW cycle. The output port is controlled in a similar manner by a free-running read clock (CKR) and a read enable pin (ENR). The read (CKR) and write (CKW) clocks may be tied together for single-clock operation or the two clocks may be run independently for asynchronous read/write appli- cations. Clock frequencies up to 83.3 MHz are achievable in the stan- dalone configuration, and up to 83.3 MHz is achievable when FIFOs are cascaded for depth expansion. Depth expansion is possible using the cascade input (XI) and cascade output (XO). The XO signal is connected to the XI of the next device, and the XO of the last device should be connected to the XI of the first device. In standalone mode, the input (XI) pin is simply tied to VSS. In the standalone and width expansion configurations, a LOW on the retransmit (RT) input causes the FIFOs to retransmit the data. Read enable (ENR) and the write enable (ENW) must both be HIGH during the retransmit, and then ENR is used to access the data. Logic Block Diagram CKW ENW WRITE CONTROL MR FL/RT WRITE POINTER RESET LOGIC XI EXPANSION LOGIC RETRANSMIT LOGIC D0 – 8 INPUT REGISTER PARITY RAM ARRAY 512x 9 2048x 9 4096x9 FLAG/PARITY PROGRAM REGISTER FLAG LOGIC READ POINTER HF E/F PAFE/XO TRI–STATE OUTPUT REGISTER OE Q0–7,Q8/PG/PE READ CONTROL CKR ENR C451-1 Pin Configurations PLCC/LCC Top View D0 D1 D2 D3 D4 D5 D6 XI ENW CKW VCC VSS HF E/F PAFE/XO Q0 4 3 2 1 32 31 30 5 29 6 28 7 8 9 10 7C451 7C453 7C454 27 26 25 24 11 23 12 22 13 21 14 15 16 17 1819 20 D7 D8 FL/RT MR VSS CKR ENR OE Q8 /PG/PE Q1 Q2 Q3 Q4 Q5 Q6 Q7 C451-2 www.DataSheet4U.com Cypress Semiconductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600 wwDwo.DcautmaSehnete#t4: U3.8c-o0m6033 Rev. A Revised December 27, 2002 www.DataSheet4U.com 1 page CY7C451 CY7C453 CY7C454 AC Test Loads and Waveforms[8, 9, 10, 11, 12] 5V OUTPUT R1500 Ω Equivalent to: CL INCLUDING JIG AND SCOPE R2 333Ω C451-4 THÉVENIN EQUIVALENT 200Ω OUTPUT 2V 3.0V GND < 3 ns ALL INPUT PULSES 90% 10% 90% 10% < 3 ns C451-5 Switching Characteristics Over the Operating Range[13] 7C451-12 7C453-12 7C454-12 7C451-14 7C453-14 7C454-14 7C451-20 7C453-20 7C454-20 7C451-30 7C453-30 7C454-30 Parameter Description Min. Max. Min. Max. Min. Max. Min. Max. Unit tCKW Write Clock Cycle 12 14 20 30 ns tCKR Read Clock Cycle 12 14 20 30 ns tCKH Clock HIGH 5 6.5 9 12 ns tCKL tA[14] Clock LOW Data Access Time 5 6.5 9 12 ns 9 10 15 20 ns tOH Previous Output Data Hold After Read HIGH 0 0 0 0 ns tFH Previous Flag Hold After Read/Write HIGH 0 0 0 0 ns tSD Data Set-Up 4 5 6 7 ns tHD Data Hold 0 0 0 0 ns tSEN Enable Set-Up 4 5 6 7 ns tHEN Enable Hold 0 0 0 0 ns tOE tOLZ[7,15] tOHZ[7,15] OE LOW to Output Data Valid OE LOW to Output Data in Low Z OE HIGH to Output Data in High Z 9 10 15 20 ns 0 0 0 0 ns 9 10 15 20 ns tPG Read HIGH to Parity Generation 9 10 15 20 ns tPE Read HIGH to Parity Error Flag 9 10 15 20 ns tFD tSKEW1[16] Flag Delay Opposite Clock After Clock 9 10 15 20 ns 0 0 0 0 ns Notes: 8. CL = 30 pF for all AC parameters except for tOHZ. 9. CL = 5 pF for tOHZ. 10. All AC measurements are referenced to 1.5V except tOE, tOLZ, and tOHZ. 11. tOE and tOLZ are measured at ± 100 mV from the steady state. 12. tOHZ is measured at +500 mV from VOL and – 500 mV from VOH. 13. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and output loading as shown in AC Test Loads and Waveforms and capacitance as in notes 8 and 9, unless otherwise specified. 14. Access time includes all data outputs switching simultaneously. 15. At any given temperature and voltage condition, tOLZ is greater than tOHZ for any given device. 16. tSKEW1 is the minimum time an opposite clock can occur after a clock and still be guaranteed not to be included in the current clock cycle (for purposes of flag update). If the opposite clock occurs less than tSKEW1 after the clock, the decision of whether or not to include the opposite clock in the current clock cycle is arbitrary. Note: The opposite clock is the signal to which a flag is not synchronized; i.e., CKW is the opposite clock for Empty and Almost Empty flags, CKR is the opposite clock for the Almost Full, Half Full, and Full flags. The clock is the signal to which a flag is synchronized; i.e., CKW is the clock for the Half Full, Almost Full, and Full flags, CKR is the clock for Empty and Almost Empty flags. Document #: 38-06033 Rev. A Page 5 of 24 5 Page CY7C451 CY7C453 CY7C454 Switching Waveforms (continued) [22,30,31,32] Write to Half Full Timing Diagram with Free-Running Clocks COUNT CKW 1024 [256] 1025 [257] W1 ENABLED WRITE 1024 [256] W2 1023 [255] W3 1024 [256] W4 ENABLED WRITE 1025 [257] W5 ENABLED WRITE 1026 [258] W6 ENABLED WRITE ENW tSKEW1 tSKEW2 CKR R1 R2 R3 R4 R5 R6 ENABLED ENABLED READ READ ENR HF E/F PAFE HIGH HIGH tFD tFD tFD C451-15 [22,30,31,32,33,34] Write to Half Full Timing Diagram with Write Flag Update Cycle with Free-Running Clocks COUNT 1024 1025 [256] [257] 1024 [256] 1023 [255] 1023 (no change) [255] FLAG UPDATE CYCLE 1024 [256] 1025 [257] 1026 [258] CKW W1 ENABLED WRITE W2 W3 W4 W5 W6 W7 FLAG ENABLED ENABLED ENABLED UPDATE WRITE WRITE WRITE WRITE ENW tSKEW1 tSKEW2 CKR R1 R2 ENABLED R3 ENABLED R4 R5 R6 R7 READ READ ENR HF HIGH E/F PAFE HIGH tFD tFD tFD C451-16 Notes: 30. CKW is clock and CKR is opposite clock. 31. Count = 2,049 indicates Half Full for the CY7C454, count=1,025 indicates Half Full for the CY7C453, and count = 257 indicates Half Full for the CY7C451. Values for CY7C451 count are shown in brackets. 32. When the FIFO contains 2048[1024,256] words, the rising edge of the next enabled write causes the HF to be true (LOW). 33. The HF write flag update cycle does not affect the count because ENW is HIGH. It only updates HF to HIGH. 34. When making the transition from Half Full to Less Than Half Full, the count must decrease by two (1,025 =>1,023; two enabled reads: R2 and R3) before a write (W4) can update flags to less than Half Full. Document #: 38-06033 Rev. *A Page 11 of 24 11 Page

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