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부품번호 MC33888 기능
기능 Quad High-Side and Octal Low-Side Switch for Automotive
제조업체 Motorola Semiconductors
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MC33888 데이터시트, 핀배열, 회로
MOTOROLA
Freescale Semiconductor, Inc.
SEMICONDUCTOR TECHNICAL DATA
Document order number: MC33888
Rev 3.0, 10/2004
Product Preview
Quad High-Side and Octal Low-Side
Switch for Automotive
The 33888 is a single-package combination of a power die with four
discrete high-side MOSFETs (two 10 mand two 40 mΩ) and an integrated
IC control die consisting of eight low-side drivers (600 meach) with
appropriate control, protection, and diagnostic features.
Programming, control, and diagnostics are accomplished using a 16-bit SPI
interface. Additionally, each high-side output has its own parallel input for
pulse-width modulation (PWM) control if desired. The low sides share a single
configurable direct input.
The 33888 is available in two power packages.
Features
• Dual 10 mHigh Side, Dual 40 mHigh Side, Octal 600 mLow Side
• Full Operating Voltage of 6.0 V to 27 V
• SPI Control of High-Side Overcurrent Limit, High Side Current Sense,
Output OFF Open Load Detection, Output ON/OFF Control, Watchdog
Timeout
• SPI Reporting of Program Status and Fault
• High-Side Analog Current Feedback with Selectable Ratio
• Enhanced 16 V Reverse Polarity VPWR Protection
33888
33888A
SOLID STATE RELAY FOR
AUTOMOTIVE APPLICATIONS
Bottom View
PNB SUFFIX
APNB SUFFIX
CASE 1438-06
36-TERMINAL PQFN
(12 x 12)
Top View
FB SUFFIX
CASE 1315-03
64-TERMINAL PQFP
ORDERING INFORMATION
Device
Temperature
Range (TA)
Package
PC33888PNB/R2
PC33888APNB/R2
-40°C to 125°C
36 PQFN
MC33888FB/R2
64 PQFP
+5.0 V
33888 Simplified Application Diagram
VPWR
+5.0 V
8 x Relay or LED
4
MCU
A/D
A/D
4
33888
FS VDD
VPWR
IHS0:IHS3
ILS
LS4:LS11
RST
SPI HS3
WDIN
HS2
CSNS2-3
CSNS0-1
FSI GND
HS1
HS0
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
www.DataSheet4U.com
© Motorola, Inc. 2004
For More Information On This Product,
Go to: www.freescale.com
www.DataSheet4U.com
Loads
www.DataSheet4U.com




MC33888 pdf, 반도체, 판매, 대치품
Freescale Semiconductor, Inc.
TERMINAL DEFINITIONS FOR PQFN (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
14 SO
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
16 CS
Chip Select
(Active Low)
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
17 SCLK
Serial Clock
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
18 SI
Serial Input
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
19 ILS
Low-Side Input
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
21 IHS3
22 IHS2
30 IHS0
31 IHS1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Each high-side input terminal is used to directly control only one designated high-
side output. These inputs may or may not be activated depending on the configured
state of the internal logic.
23 CSNS2-3
29 CSNS0-1
Current Sense 2-3
Current Sense 0-1
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
25 HS3
28 HS2
High-Side Output 3
High-Side Output 2
Each terminal is the source of a 40 mMOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
26 HS1
27 HS0
High-Side Output 1
High-Side Output 0
Each terminal is the source of a 10 mMOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS0 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
33 WAKE
Wake
This terminal is used to input a logic [1] signal in order to enable the watchdog timer
function. An internal clamp protects the terminal from high voltages when current is
limited with an external resistor. This input has a passive internal pulldown.
33888
4
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com

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MC33888 전자부품, 판매, 대치품
Freescale Semiconductor, Inc.
TERMINAL DEFINITIONS FOR PQFP (continued)
Functional descriptions of many of these terminals can be found in the System/Application Information section beginning on
page 19.
Terminal
Terminal
Name
Formal Name
Definition
7 LS5
Low-Side Output 5
Each low-side terminal is one 0.6 low-side output MOSFET drain, which pulls
10 LS7
Low-Side Output 7
current through the connected loads. Each of the outputs is actively clamped at
13 LS9
Low-Side Output 9
53 V. These outputs are current and thermal overload protected. Maximum steady
16 LS11
Low-Side Output 11
state current through each of these outputs is 800 mA.
17 VDD Digital Drain Voltage (Power) This is an external input terminal used to supply power to the SPI circuit.
18 SO
Serial Output
This is an output terminal connected to the SPI Serial Data Input terminal of the
MCU or to the SI terminal of the next device in a daisy chain. This output will remain
tri-stated unless the device is selected by a low CS terminal. The output signal
generated will have CMOS logic levels and the output data will transition on the
rising edges of SCLK. The serial output data provides fault information for each
output and is returned MSB first when the device is addressed. OD11 through OD0
are output fault bits for outputs 11 through 0, respectively.
19 CS
Chip Select
(Active Low)
This is an input terminal connected to a chip select output of a microcontroller
(MCU). This IC controls which device is addressed (selected) by pulling the CS
terminal of the desired device logic Low, enabling the SPI communication with the
device, while other devices on the serial link keep their serial outputs tri-stated. This
input has an internal active pullup and requires CMOS logic levels.
20 SCLK
Serial Clock
This input terminal is connected to the SCLK terminal of the master MCU, which is
a bit (shift) clock for the SPI port. It transitions one time per bit transferred at an
operating frequency, fSPI, and is idle between command transfers. It is 50% duty
cycle and has CMOS logic levels. This signal is used to shift data to and from the
33888.
21 SI
Serial Input
This input terminal is connected to the SPI Serial Data Output terminal of the MCU
from which it receives output command data. This input has an internal active
pull-down and requires CMOS logic levels. The serial data transmitted on this line
is a 16-bit control command sent MSB first, which controls the twelve output
channels. Bits D3:D0 control the high-side outputs HS3:HS0, respectively. Bits
D11:D4 control the low-side outputs LS11:LS4, respectively. The MUC will ensure
that data is available on the falling edge of SCLK.
22 ILS
Low-Side Input
This input terminal is used to directly control a number of the low-side devices as
configured by SPI. This terminal may or may not be activated depending on the
configured state of the internal logic.
23 IHS3
24 IHS2
61 IHS0
62 IHS1
High-Side Input 3
High-Side Input 2
High-Side Input 0
High-Side Input 1
Each high-side input terminal is used to directly control only one designated high-
side output. These inputs may or may not be activated depending on the configured
state of the internal logic.
25 CSNS2-3
60 CSNS0-1
Current Sense 2-3
Current Sense 0-1
These terminals deliver a ratioed amount of the high-side output current that can be
used to generate signal ground referenced output voltages for use by the MCU.
Each respective CSNS terminal can be configured via SPI to deliver current from
either of the two assigned outputs, or the currents could be the sum of the two.
Current from HS0 and/or HS1 are sensed via CSNS0-1. Current from HS2 and/or
HS3 are sensed via CSNS2-3.
28, 29
56, 57
HS3
HS2
High-Side Output 3
High-Side Output 2
Each terminal is the source of a 40 mMOSFET high-side driver, which delivers
current through the connected loads. These outputs can be controlled via SPI or
using the IHS terminals depending on the internal configuration. These outputs are
current limited and thermally protected. During fail-safe mode, output HS2 will be
turned on until the device is reinitialized and then immediately followed by normal
operation.
30 – 35,
50 – 55
NC
Not Connected
These terminals are not connected internally.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
For More Information On This Product,
Go to: www.freescale.com
33888
7

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