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PDF MC33882 Data sheet ( Hoja de datos )

Número de pieza MC33882
Descripción Six-Output Low-Side Switch with SPI and Parallel Input Control
Fabricantes Motorola Semiconductors 
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Advance Information
Six-Output Low-Side Switch with
SPI and Parallel Input Control
The 33882 is a smart six-output low-side switch able to control system loads
up to 1.0 A. The six outputs can be controlled via both serial peripheral
interface (SPI) and parallel input control, making the device attractive for fault-
tolerant system applications. There are two additional 30 mA low-side
switches with SPI diagnostic reporting (with parallel input control only).
The 33882 is designed to interface directly with industry-standard
microcontrollers via SPI to control both inductive and incandescent loads.
Outputs are configured as open-drain power MOSFETs incorporating internal
dynamic clamping and current limiting. The device has multiple monitoring and
protection features, including low standby current, fault status reporting,
internal 52 V clamp on each output, output-specific diagnostics, and protective
shutdown. In addition, it has a mode select terminal affording a dual means of
input control.
Features
• Outputs Clamped for Switching Inductive Loads
• Very Low Operational Bias Currents (< 2.0 mA)
• CMOS Input Logic Compatible with 5.0 V Logic Levels
• Load Dump Robust (60 V Transient at VPWR on OUT0–OUT5)
• Daisy Chain Operation of Multiple Devices Possible
• Switch Outputs Can Be Paralleled for Higher Currents
• RDS(ON) of 0.4 per Output (25°C) at 13 V VPWR
• SPI Operation Guaranteed to 2.0 MHz
Document order number: MC33882/D
Rev 3.0, 12/2003
33882
SIX-OUTPUT LOW-SIDE SWITCH
DH SUFFIX
CASE 979A-09
30-TERMINAL HSOP
FC SUFFIX
CASE 1306-01
32-TERMINAL QFN
ORDERING INFORMATION
Device
MC33882DH/R2
MC33882FC/R2
Temperature
Range (TA)
-40°C to 125°C
-40°C to 125°C
Package
30 HSOP
32 QFN
3388S2imSpimlifipedlifAiepdpliAcaptpiolnicDaitaiogrnamDiagram
VDD VPWR
MCU
Optional Parallel
Control of
Outputs 0 through 7
33882
VPWR
VDD
CS
SCLK
SI
SO
IN0
IN1
IN2
IN3
IN4
IN5
IN6
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
IN0 & IN1
IN2 & IN3
IN4 & IN5
MODE
GND
IN7
Optional Control
of Paired Outputs
High-Power
Outputs
Low-Power
LED
Outputs
This document contains certain information on a new product.
Specifications and information herein are subject to change without notice.
www.DataSheet4U.com
© Motorola, Inc. 2003
www.DataSheet4U.com
www.DataSheet4U.com

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MC33882 pdf
Transparent Top View of Package
IN4 & IN5
IN6
OUT6
GND
GND
VPWR
IN0 & IN1
MODE
1
2
3
4
5
6
7
8
24 OUT7
23
22
VDD
GND
21 GND
20 GND
19
GND
18 SO
17
CS
QFN TERMINAL FUNCTION DESCRIPTION
Terminal
Terminal
Name
Formal Name
7
IN0 & IN1
Input 0 & Input 1
26
IN2 & IN3
Input 2 & Input 3
1
IN4 & IN5
Input 4 & Input 5
2
9
11
13
25
28
30
32
3
10
12
14
24
27
29
31
4, 5, 19–22
6
8
15
IN6
IN0
IN1
IN2
IN7
IN3
IN4
IN5
OUT6
OUT0
OUT1
OUT2
OUT7
OUT3
OUT4
OUT5
GND
VPWR
MODE
SI
Input 0–Input 7
Output 0–Output 7
Ground
Load Supply Voltage
Mode Select
Serial Input
Definition
These input terminals control two output channels each when the MODE terminal is
pulled high. These terminals may be connected to pulse width modulated (PWM)
outputs of the control IC while the MODE terminal is high. The states of these terminals
are ignored during normal operation (MODE terminal low) and override the normal
inputs (serial or parallel) when the MODE terminal is high. These terminals have internal
active 25 µA pull-downs.
These are parallel input terminals. These terminals have internal 25 µA active pull-
downs.
Each terminal is one channel's drain, sinking current for the respective load.
Ground continuity is required for the outputs to turn on.
This terminal is connected to battery voltage. A decoupling capacitor is required from
VPWR to ground.
The MODE terminal is connected to the MODE terminal of the control IC. This terminal
has an internal active 25 µA pull-up.
The Serial Input terminal is connected to the SPI Serial Data Output terminal of the
control IC from where it receives output command data. This input has an internal
active 25 µA pull-down and requires CMOS logic levels.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
5

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MC33882 arduino
DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions 4.75 V VDD 5.25 V, 9.0 V VPWR 17 V, -40°C TA 125°C unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max Unit
POWER OUTPUT TIMING
Output Rise Time (Note 25)
Output Fall Time (Note 25)
tR 1.0 – 10 µs
tF 1.0 – 10 µs
Output Turn-ON Delay Time (Note 26)
tDLY (ON)
1.0
10 µs
Output Turn-OFF Delay Time (Note 27)
Output Short Fault Sense Time (Note 28)
RLOAD = < 1.0 V
t DLY(OFF)
1.0
10 µs
tSS µs
25 – 100
Output Short Fault Refresh Time (Note 29)
RLOAD = < 1.0 V
t REF
ms
3.0 4.5 6.0
Output OFF Open Load Sense Time (Note 30)
Output ON Open Load Sense Time (Note 31)
t OS(OFF)
25
60 100 µs
t OS(ON)
3.0
12 ms
Output Short Fault ON Duty Cycle (Note 32)
SC DC
0.42
3.22 %
DIGITAL INTERFACE TIMING
SCLK Clock High Time (SCLK = 3.2 MHz) (Note 33)
t SCLKH
– 141 ns
SCLK Clock Low Time (SCLK = 3.2 MHz) (Note 33)
Falling Edge (0.8 V) of CS to Rising Edge (2.0 V) of SCLK
Required Setup Time (Note 33)
t SCLKL
t LEAD
– 141 ns
ns
– 140
Falling Edge (0.8 V) of SCLK to Rising Edge (2.0 V) of CS
Required Setup Time (Note 33)
t LAG
ns
– 50
SI, CS, SCLK Incoming Signal Rise Time (Note 33)
t RSI
– 50 ns
SI, CS, SCLK Incoming Signal Fall Time (Note 33)
tFSI – – 50 ns
Notes
25. Output Rise and Fall time measured at 10% to 90% and 90% to 10% voltage points respectively across 15 resistive load to a VBAT of
15 V, VPWR = 15 V.
26. Output Turn-ON Delay Time measured from rising edge (3.0 V) VIN (CS for serial) to 90% VO using a 15 load to a VBAT of 15 V,
VPWR = 15 V.
27. Output Turn-OFF Delay Time measured from falling edge (1.0 V) VIN (3.0 V rising edge of CS for serial) to 10% VO using a 15 load to a
VBAT of 15 V, VPWR = 15 V.
28. The shorted output is turned ON during tSS to retry and check if the short has cleared. The shorted output is in current limit during tSS. The
tSS is measured from the start of current limit to the end of current limit.
29. The Short Fault Refresh Time is the waiting period between tSS retry signals. The shorted output is disabled during this refresh time. The
tREF is measured from the end of current limit to the start of current limit.
30. The tOS(OFF) is measured from the time the faulted output is turned OFF until the fault bit is available to be loaded into the internal fault
register. To guarantee a fault is reported on SO, the falling edge of CS must occur at least 100 µs after the faulted output is off.
31. The tOS(ON) is measured from the time the faulted output is turned ON until the fault bit is available to be loaded into the internal fault register.
To guarantee a fault is reported on SO, the falling edge of CS must occur at least 12 ms after the faulted output is ON.
32. Percent Output Short Fault ON Duty Cycle is defined as (tSS) ÷ (tREF) x 100. This specification item is provided FYI and is not tested.
33. Parameter is not tested and values suggested are for system design consideration only in preventing the occurrence of double pulsing.
MOTOROLA ANALOG INTEGRATED CIRCUIT DEVICE DATA
33882
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