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PDF YMU769 Data sheet ( Hoja de datos )
| Número de pieza | YMU769 | |
| Descripción | Mobile Audio 5 Type S | |
| Fabricantes | Yamaha | |
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( DataSheet : www.DataSheet4U.com )
YMU769
MA-5S
Mobile Audio 5 Type S
PrPerleimliminianrayry
Outline
YMU769 has a virtual speaker image function, so that it is the most suitable LSI as a sound source output device
which is used in mobile phones for high functional game sounds or high quality ringing melodies, and so on.
Synthesizer section in YMU769 adopts “stereophonic hybrid synthesizer system” that is given advantages of both FM
synthesizers and Wave Table synthesizers, makes it possible to generate up to 32 FM voices and 32 Wave Table
voices simultaneously.
Since FM synthesizer is able to provide countless voices by specifying parameters with only several tens of bytes,
memory capacity and communication band can be saved, and thus, the device exhibits the features in operating
environment of mobile phones such as allowing distribution of arbitrary melodies with voices. On the other hand,
Wave Table synthesizer can pronounce the voice stored in ROM, and in addition it can handle arbitrary
ADPCM/PCM voices by sequencer. Furthermore, the Stream Playback function, and the time-variant low pass filter
function by AL (Analog Lite) Synthesizer are equipped.
YMU769 has two-channel virtual speaker image functions based on DVX technology, so that natural stereo sounds
can be realized even in an environment such as two adjacent speakers on a small body like mobile phones.
Integrated stereo speaker amplifiers make external components unnecessary and consequently it saves space.
In addition, YMU769 has a built-in circuit to control an LED or a vibrator synchronously to music, and has a power
down mode for saving supply current to a minimum.
Features
¾ Simultaneous generation up to 64 tones by stereophonic hybrid synthesizer.
¾ Equipped with time-variant low pass filter function by AL (Analog Lite) synthesizer.
¾ Stream replay with ADPCM / PCM is possible.
¾ Has built-in default voices for FM and Wave Table synthesizers in the ROM, and the voices can be
downloaded to SRAM.
¾ Has built-in SD (Stereo Dipole) function by DVX technology.
¾ Equipped with speaker amplifier and equalizer circuit.
¾ Equipped with a stereophonic output pin for headphone.
¾ Equipped with vibration control circuit, and LED lighting control circuit.
¾ Has built-in PLL and inputting of master clock up to 20 MHz is possible and supports TCXO
(Temperature Compensated Crystal Oscillator).
¾ Contains a 16-bit stereophonic D/A converter.
¾ Equipped with general-purpose I/O port (three parties)
¾ Has a function upwardly compatible to MA-5
¾ Has power down mode.
¾ Power supply for internal core
¾ Power supply for CPU I/O
¾ Power supply for speaker amplifier
¾ 48-pin QFN plastic package
2.65V ∼ 3.30V
1.65V ∼ VDD
VDD ∼ 4.50V
The contents of this booklet are target specifications and they might be changed without
notice. Please confirm the finalized specifications again before the use of this LSI.
www.DataSheet4U.com
YAMAHA CORPORATION
www.DataSheet4U.com
YMU769 CATALOG
CATALOG No : 4MU769A1
2003.10
1 page  
YMU769
CPU interface
CPU interface is an 8-bit parallel type.
It assumes that a total of 13 pins of 4 control signals (/WR, /RD, /CS, A0 pin), 8 data bus (D0 to D7), and
1 Interrupt pin (/IRQ) are connected to the external CPU.
This block controls the writing and reading of data by the input polarity of control signal.
Interface register
This register is able to access directly from the external CPU. There are 2 bytes spaces.
The latter Intermediate register can be accessed through the Interface register.
Intermediate register
This register is accessed through the Interface register.
The “Control Register” and ROM/SRAM, which describes below, can be accessed through this register.
This register is called “Intermediate register” since this exists in the middle of the Interface register and the
Control register.
In the Intermediate register, there are some registers to control various functions.
Control register, ROM/SRAM
The Control register and ROM/SRAM are accessed from “Instantaneous write register”, “Delayed write
register”, and “Instantaneous read register” in the Intermediate register.
In the Control register, there is a register to control the following synthesizer mainly.
The voice parameter for FM (GM 128 voices + DRUM 40 voices) and Wave data for WT are stored in ROM.
SRAM is used at the download of arbitrary FM voice parameter and Wave data for WT.
Moreover, it is used as storing buffer at the stream playback of PCM/ADPCM.
FIFO
This is an abbreviation of “First In First Out” means the memory which data is read in order of written.
There are 2 paths to write into FIFO in the Intermediate register.
The “Instantaneous write path” is for accessing the Control register and ROM/SRAM immediately, also
“Delayed write path” is for accessing the Control register after managing time through the sequencer.
FIFO size of Instantaneous path is 64-byte, and its size of Delayed path is 512-byte.
Sequencer
This is for interpreting the contents of data which is written into the “Delayed write path”.
Generally, “Music data” is written into the Delayed write path. It interprets the contents of music data and
controls the synthesizer after sequencer, and then plays the music.
Hybrid synthesizer
This device contains a built-in Polyphonic synthesizer that adopts a stereophonic hybrid system that generates
up to 64 tones.
FM synthesizer, WT (Wave Table) synthesizer, Stream playback, and AL (Analog Lite) synthesizer are
available.
DVX Arithmetic control
SD (Stereo Dipole) function that is based on DVX technology makes it possible to create natural stereo sound
even in using adjacent two speakers.
Preliminary
5
5 Page 
YMU769
z CPU Interface
The AC characteristics of a CPU interface are measured on condition as follows.
The input conditions at the time of measurement
The measurement points
: VIH = 0.8×IOVDD,
: VIH = 0.65×IOVDD,
VOH = 0.65×IOVDD,
VIL=0.2×IOVDD
VIL=0.35×IOVDD
VOL=0.35×IOVDD
○ CPU Interface 1 (In the case of IOVDD ≧ 2.65V)
(Write cycle)
Item
Address setup time
Address hold time
Chip select setup time
Chip select hold time
Write pulse width
Data setup time
Data hold time
TOP=-20 ∼ 85°C, VDD=IOVDD=2.65 ∼ 3.30V,
Symbol
Min
TADS
50
TADH
0
TCSS
50
TCSH
0
TWW
50
TWDS
30
TWDH
0
Capacitor load=50 pF
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
(Read cycle)
Item
Access time from /RD pin
Access time from /CS pin
Access time from /A0 pin
Data hold time from /RD pin
Data hold time from /CS pin
Data hold time from A0 pin
High-impedance transition time from /RD pin
High-impedance transition time from /CS pin
TOP=-20 ∼ 85°C, VDD=IOVDD=2.65 ∼ 3.30V,
IOH= -1.0mA, IOL= +1.0mA (D0 ∼ D7 pin)
Symbol
Min
TACCRD
TACCCS
TACCA0
TDHRD
0
TDHCS
0
TDHA0
0
TDZRD
TDZCS
Capacitor load=50 pF
Max.
70
70
70
30
30
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Preliminary
11
11 Page | ||
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| PDF Descargar | [ Datasheet YMU769.PDF ] | |
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