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PDF BGB101 Data sheet ( Hoja de datos )
| Número de pieza | BGB101 | |
| Descripción | 0 dBm Bluetooth radio module | |
| Fabricantes | NXP Semiconductors | |
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( DataSheet : www.DataSheet4U.com )
DISCRETE SEMICONDUCTORS
DATA SHEET
BGB101
0 dBm Bluetooth radio module
Preliminary specification
2003 Aug 05
www.DataSheet4U.com
www.DataSheet4U.com
1 page  
Philips Semiconductors
0 dBm Bluetooth radio module
Preliminary specification
BGB101
The output stage of the transmit chain active part is balanced, for reduced spurious emissions (EMC). It is connected
through a balun (balanced-to-unbalanced) circuit to the TX/RX switch. This switch is controlled by internal logic circuits
in the active die. The balun circuit has built-in selectivity, to further reduce out-of-band spurious emissions.
The output amplifier of the IC is switched on by pulling the DCXCTR control line high. This can be done before the S_EN
line goes low. In this mode, the PLL compensates for the frequency jump (pulling) that might otherwise be caused by
switching the output amplifier on when the PLL would already have been de-activated.
The DCXCTR line should be kept high during the entire TX slot.
The output power level is programmable with a dynamic range of approximately 19 dB with a maximum step size of 4 dB.
In this way, a simple power amplifier can be added in the application with power control implemented by reducing the
pre-amplifier gain.
Receive mode
Also the receiver functionality is fully integrated. It is a near-zero-IF (1 MHz) architecture with active image rejection.
The integrated channel filters use a build-in auto calibration scheme, providing an excellent sensitivity over a wide
temperature range. The sensitive RX input of the active die is a balanced configuration, in order to reduce unwanted
(spurious) responses. The balun structure to convert from unbalanced to balanced signals has built-in selectivity. This
suppresses GSM-900 frequencies by more than 40 dB. For better immunity to DCS, DECT, GSM-1800 and W_CDMA
signals, an extra band-pass filter has been included.
The synthesizer PLL may be switched off during demodulation. This reduces the effects that reference frequency
breakthrough may have on receiver sensitivity and adjacent channel selectivity, and also reduces the power
consumption. The demodulator contains an advanced DC offset compensation circuit. This reduces the effects of
frequency mismatch between (remote) transmitter and receiver. These may be caused by differences in reference
frequency, but also by frequency drift during open-loop modulation and demodulation.
Because the VCO is directly modulated by the signal present at the T_GFSK pin, this pin should be connected to a
well-defined and stable DC bias voltage, also when in RX mode. Moreover, this bias voltage should already be present
during the S_EN programming pulse. In this way, the PLL can correct for possible frequency offsets that might otherwise
occur.
The demodulated RF signal is compared against a reference (slicer) value and then output. This reference voltage is
derived from the demodulated output signal itself, by the DC extractor circuit. It operates in three subsequent phases,
controlled by the DCXCTR signal:
• In the first phase, during the preamble and the early part of the Access Code, a Min/Max detector provides a crude but
fast estimate of the required DC voltage. The DCXCTR line should be low during this phase.
• When the DCXCTR line is pulled high, this crude estimate is used as an initial guess for an integrator circuit that
provides an accurate estimate of the required DC voltage. This is the second phase. The DC value obtained is derived
from the Barker sequence and the trailer, which together make up the final 10 bits of the Access Code. The DCXCTR
line should be pulled high 20 µs before the trailer sequence is expected to end (there is a ±10 µs timing uncertainty
between the expected and the actual end of the trailer sequence).
• Exactly at the end of the trailer, the DCXCTR must be pulled low again. The device now enters the third phase, during
which the estimate of the offset voltage that was obtained during phases one and two is retained. A small and slow
variation to compensate carrier frequency drift can still be tracked.
An RSSI output with a high dynamic range of more than 50 dB provides near-instantaneous information on the quality
of the signal received.
Due to the IF frequency at 1 MHz, in RX mode the VCO frequency should be 1 MHz higher than the channel frequency.
This should be taken care of by the baseband controller.
Power-down mode
In Power-down mode, current consumption is reduced to 5 µA (typical). The 3-wire bus inputs present a high-ohmic
resistance to ground.
2003 Aug 05
5
5 Page 
Philips Semiconductors
0 dBm Bluetooth radio module
Preliminary specification
BGB101
SYMBOL
PARAMETER
CONDITIONS
MIN. TYP. MAX. UNIT
out of band blocking
(see also figure
FTLOrf
spurious emissions
LO to RF feedthrough
wanted signal −67dBm; CW
interferer level
range 30 MHz to 2 GHz
0
range 2 GHz to 2400 MHz −27
range 2500 MHz to 3 GHz −27
range 3 GHz to 12.75 GHz 0
wanted signal −67dBm; GSM +20
modulated signal between 880
and 915 MHz (GSM−900 uplink)
wanted signal −67dBm; GSM
modulated signal between 1785
and 1800 MHz (GSM−1800
uplink)
+20
30 MHz to 1 GHz; note 5
−
1 GHz to 12.75 GHz; note 5
−
measured at 2450MHz
−
−
−
−
−
−
−
tbd
tbd
tbd
− dBm
− dBm
− dBm
− dBm
− dBm
− dBm
−36 dBc
−30 dBc
−47 dBc
Interface (logic) inputs and outputs; pins S_DATA, S_CLK, S_EN, DCXCTR, T_EN, R_DATA, T_GFSK
VIH
VIL
Ibias
fS_CLKmax
tS_ENmin
VOH
VOL
RR_DATA, load
HIGH-level input voltage
note 3
LOW-level input voltage
input bias current
HIGH or LOW level
maximum 3-wire bus frequency note 4
minimum S_EN pulse duration to switch off the module: note 3
HIGH-level output voltage
for R_DATA output
LOW-level output voltage
for R_DATA output
real part of the R_DATA load
admittance
at 500 kHz
1.4
−0.3
−5
−
1
1.6
−0.3
−
−
−
−
−
−
1.7
−
tbd
VS
+0.4
+5
5
−
1.8
+0.4
−
V
V
µA
MHz
µs
V
V
Ω
CR_DATA, load imaginary part of the R_DATA at 500 kHz
load admittance
− 10 30 pF
VT_GFSK,DC
RT_GFSK,in
T_GFSK DC voltage
real part of the T_GFSK input
admittance
note 2
at 500 kHz
− tbd − V
− tbd − Ω
CT_GSFK, in
imaginary part of the T_GFSK at 500 kHz
input admittance
− tbd − pF
Notes
1. The actual VCO frequency is double the programmed frequency. It is divided by 2 internally.
2. T_GFSK is DC coupled. The DC voltage must be supplied by the baseband processor.
3. VIH should never exceed 3.6V.
4. See detailed timing information.
5. Over full temperature and supply voltage range.
6. In combination with the BlueBerry Baseband processor.
7. Packet Error Rate (PER): lost Packets due to access code or Packet-header failure.
2003 Aug 05
11
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet BGB101.PDF ] | |
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