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부품번호 GVT7C1367A 기능
기능 (GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM
제조업체 Cypress Semiconductor
로고 Cypress Semiconductor 로고


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GVT7C1367A 데이터시트, 핀배열, 회로
( DataSheet : www.DataSheet4U.com )
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
256K x 36/512K x 18 Pipelined SRAM
Features
• Fast access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Fast clock speed: 225 MHz, 200 MHz, 166 MHz, and
150 MHz
• Fast OE access times: 2.5 ns, 3.0 ns, and 3.5 ns
• Optimal for performance (two cycle chip deselect, depth
expansion without wait state)
• 3.3V –5% and +10% power supply
• 3.3V or 2.5V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Multiple chip enables for depth expansion:
three chip enables for TA(GVTI)/A(CY) package version
and two chip enables for B(GVTI)/BG(CY) and
T(GVTI)/AJ(CY) package versions
• Address pipeline capability
• Address, data and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst
sequence)
• Automatic power-down for portable applications
• JTAG boundary scan for B and T package version
• Low profile 119-bump, 14-mm x 22-mm PBGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced
triple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
The CY7C1366A/GVT71256C36 and CY7C1367A/
GVT71512C18 SRAMs integrate 262,144 x 36 and 524,288 x
18 SRAM cells with advanced synchronous peripheral circuitry
and a 2-bit counter for internal burst operation. All synchro-
nous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (BWa, BWb, BWc, BWd, and BWE), and Global Write
(GW). However, the CE2 Chip Enable input is only available for
the TA(GVTI)/A(CY) package version.
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate a self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide, as controlled by the write control inputs.
Individual byte write allows an individual byte to be written.
BWa controls DQa. BWb controls DQb. BWc controls DQc.
BWd controls DQd. BWa, BWb, BWc, and BWd can be active
only with BWE being LOW. GW being LOW causes all bytes
to be written. The x18 version only has 18 data inputs/outputs
(DQa and DQb) along with BWa and BWb (no BWc, BWd,
DQc, and DQd).
For the B(GVTI)/BG(CY) and T(GVTI)/AJ(CY) package ver-
sions, four pins are used to implement JTAG test capabilities:
Test Mode Select (TMS), Test Data-In (TDI), Test Clock (TCK),
and Test Data-Out (TDO). The JTAG circuitry is used to serially
shift data to and from the device. JTAG inputs use
LVTTL/LVCMOS levels to shift data during this testing mode of
operation. The TA package version does not offer the JTAG
capability.
The CY7C1366A/GVT71256C36 and CY7C1367A/
GVT71512C18 operate from a +3.3V power supply. All inputs
and outputs are LVTTL compatible.
Selection Guide
7C1366A-225/
71256C36-4.4
7C1367A-225/
71512C18-4.4
Maximum Access Time (ns)
2.5
Maximum Operating Current (mA)
Commercial
570
Maximum CMOS Standby Current (mA)
10
7C1366A-200/
71256C36-5
7C1367A-200/
71512C18-5
3.0
510
10
7C1366A-166/
71256C36-6
7C1367A-166/
71512C18-6
3.5
425
10
7C1366A-150/
71256C36-6.7
7C1367A-150/
71512C18-6.7
3.5
380
10
www.DataSheet4U.com
wwwC.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
June 12, 2001




GVT7C1367A pdf, 반도체, 판매, 대치품
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
Pin Configurations (continued)
1
A VCCQ
B NC
C NC
D DQc
E DQc
F VCCQ
G DQc
H DQc
J VCCQ
K DQd
L DQd
M VCCQ
N DQd
P DQd
R NC
T NC
U VCCQ
1
A VCCQ
B NC
C NC
D DQb
E NC
F VCCQ
G NC
H DQb
J VCCQ
K NC
L DQb
M VCCQ
N DQb
P NC
R NC
T NC
U VCCQ
2
A
CE2
A
DQc
DQc
DQc
DQc
DQc
VCC
DQd
DQd
DQd
DQd
DQd
A
NC
TMS
2
A
CE2
A
NC
DQb
NC
DQb
NC
VCC
DQb
NC
DQb
NC
DQb
A
A
TMS
119-Ball BGA
Top View
256Kx36
34
A ADSP
A ADSC
A
VSS
VSS
VSS
BWc
VCC
NC
CE
OE
ADV
VSS
NC
VSS
BWd
GW
VCC
CLK
NC
VSS
VSS
VSS
MODE
A
BWE
A1
A0
VCC
A
TDI TCK
512Kx18
3
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
VSS
VSS
VSS
VSS
MODE
A
TDI
4
ADSP
ADSC
VCC
NC
CE
OE
ADV
GW
VCC
CLK
NC
BWE
A1
A0
VCC
NC
TCK
5
A
A
A
VSS
VSS
VSS
BWb
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
5
A
A
A
VSS
VSS
VSS
VSS
VSS
NC
VSS
BWa
VSS
VSS
VSS
NC
A
TDO
6
A
A
A
DQb
DQb
DQb
DQb
DQb
VCC
DQa
DQa
DQa
DQa
DQa
A
NC
NC
6
A
CE2
A
DQa
NC
DQa
NC
DQa
VCC
NC
DQa
NC
DQa
NC
A
A
NC
7
VCCQ
NC
NC
DQb
DQb
VCCQ
DQb
DQb
VCCQ
DQa
DQa
VCCQ
DQa
DQa
NC
ZZ
VCCQ
7
VCCQ
NC
NC
NC
DQa
VCCQ
DQa
NC
VCCQ
DQa
NC
VCCQ
NC
DQa
NC
ZZ
VCCQ
4

4페이지










GVT7C1367A 전자부품, 판매, 대치품
CY7C1366A/GVT71256C36
CY7C1367A/GVT71512C18
512K X 18 Pin Descriptions (continued)
X18 PBGA Pins X18 QFP Pins Name
Type
Description
2B
97
CE2
Input-
Chip Enable: This active HIGH input is used to enable the
Synchronous device.
(not available for
PBGA)
92 (for TA Ver-
sion only)
CE2
Input-
Chip Enable: This active LOW input is used to enable the de-
Synchronous vice. Not available for B and T package versions.
4F
86
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
4G
83
ADV
Input-
Address Advance: This active LOW input is used to control the
Synchronous internal burst counter. A HIGH on this pin generates wait cycle
(no address advance).
4A
84
ADSP
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be registered
and a Read cycle is initiated using the new address.
4B
85
ADSC
Input-
Address Status Controller: This active LOW input causes de-
Synchronous vice to be deselected or selected along with new external ad-
dress to be registered. A Read or Write cycle is initiated de-
pending upon write control inputs.
3R
31
MODE
Input-
Mode: This input selects the burst sequence. A LOW on this
Static
pin selects Linear Burst. A NC or HIGH on this pin selects
Interlinear Burst.
7T
64
ZZ
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
(a) 6D, 7E, 6F, 7G, (a) 58, 59, 62, 63,
6H, 7K, 6L, 6N, 7P 68, 69, 72, 73, 74
(b) 1D, 2E, 2G, 1H, (b) 8, 9, 12, 13,
2K, 1L, 2M, 1N, 2P 18, 19, 22, 23, 24
DQa
DQb
Input/
Output
Data Inputs/Outputs: Low Byte is DQa. High Byte is DQb. Input
data must meet set up and hold times around the rising edge
of CLK.
2U
38
TMS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. Not available for
3U 39 TDI
TA package version.
4U 43 TCK
for B and T
version
5U
42
TDO
Output IEEE 1149.1 test output. LVTTL-level output. Not available for
for B and T
TA package version.
version
4C, 2J, 4J, 6J, 4R 15, 41,65, 91
3D, 5D, 3E, 5E, 3F,
5F, 5G, 3H, 5H, 3K,
5K, 3L, 3M, 5M,
3N, 5N, 3P, 5P
5, 10, 17, 21, 26,
40, 55, 60, 67,
71, 76, 90
VCC
VSS
Supply
Ground
Core power Supply: +3.3V 5% and +10%
Ground: GND.
1A, 7A, 1F, 7F, 1J, 4, 11, 20, 27, 54, VCCQ
7J, 1M, 7M, 1U, 7U 61, 70, 77
I/O Supply Output Buffer Supply: +2.5V or +3.3V.
1B, 7B, 1C, 7C, 2D, 1-3, 6, 7, 14, 16,
4D, 7D, 1E, 6E, 2F, 25, 28-30, 51-53,
1G, 6G, 2H, 7H, 56, 57, 66, 75,
3J, 5J, 1K, 6K, 2L, 78, 79, 80, 95, 96
4L, 7L, 6M, 2N, 7N,
1P, 6P, 1R, 5R, 7R, 38, 39, 42 for TA
1T, 4T, 6U
Version
NC
- No Connect: These signals are not internally connected. User
can leave it floating or connect it to VCC or VSS.
7

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GVT7C1367A

(GVT7xxxx) 256K X 36/512K X 18 Pipelined SRAM

Cypress Semiconductor
Cypress Semiconductor

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