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부품번호 GVT71256T18 기능
기능 (GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM
제조업체 Cypress Semiconductor
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GVT71256T18 데이터시트, 핀배열, 회로
( DataSheet : www.DataSheet4U.com )
327
CY7C1359A/GVT71256T18
256K x 18 Synchronous-Pipelined Cache Tag RAM
Features
• Fast match times: 3.5, 3.8, 4.0 and 4.5 ns
• Fast clock speed: 166, 150, 133, and 100 MHz
• Fast OE access times: 3.5, 3.8, 4.0 and 5.0 ns
• Pipelined data comparator
• Data input register load control by DEN
• Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
• 3.3V –5% and +10% core power supply
• 2.5V or 3.3V I/O supply
• 5V tolerant inputs except I/Os
• Clamp diodes to VSS at all inputs and outputs
• Common data inputs and data outputs
• JTAG boundary scan
• Byte Write Enable and Global Write control
• Three chip enables for depth expansion and address
pipeline
• Address, data, and control registers
• Internally self-timed Write Cycle
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• Low-profile JEDEC standard 100-pin TQFP package
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low power CMOS designs using advanced tri-
ple-layer polysilicon, double-layer metal technology. Each
memory cell consists of four transistors and two high valued
resistors.
All synchronous inputs are gated by registers controlled by a
positive-edge-triggered Clock Input (CLK). The synchronous
inputs include all addresses, all data inputs, address-pipelin-
ing Chip Enable (CE), depth-expansion Chip Enables (CE2
and CE2), Burst Control Inputs (ADSC, ADSP, and ADV), Write
Enables (WEL, WEH, and BWE), Global Write (GW), and Data
Input Enable (DEN).
Asynchronous inputs include the Burst Mode Control (MODE),
the Output Enable (OE) and the Match Output Enable (MOE).
The data outputs (Q) and Match Output (MATCH), enabled by
OE and MOE respectively, are also asynchronous.
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance pin (ADV).
Data inputs are registered with Data Input Enable (DEN) and
chip enable pins (CE, CE2, and CE2). The outputs of the data
input registers are compared with data in the memory array
and a match signal is generated. The match output is gated
into a pipeline register and released to the match output pin at
the next rising edge of Clock (CLK).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to two bytes wide as controlled by the write control inputs. In-
dividual byte write allows individual byte to be written. WEL
controls DQ1DQ9. WEH controls DQ10DQ18. WEL and
WEH can be active only with BWE being LOW. GW being LOW
causes all bytes to be written.
The CY7C1359C/GVT71256T18 operates from a +3.3V pow-
er supply with output power supply being +2.5V or +3.3V. All
inputs and outputs are LVTTL compatible. The device is ideally
suited for address tag RAM for up to 8 MB secondary cache.
Selection Guide
Maximum Access Time (ns)
Maximum Operating Current (mA)
Maximum CMOS Standby Current (mA)
7C1359A-166
71256T36-6
3.5
310
20
7C1359A-150
71256T36-6.7
3.8
275
20
7C1359A-133
71256T36-7.5
4.0
250
20
7C1359A-100
71256T36-10
4.5
190
20
www.DataSheet4U.com
wwCw.yDparteaSssheSeet4mU.iccoomnductor Corporation • 3901 North First Street • San Jose • CA 95134 • 408-943-2600
Document #: 38-05120 Rev. **
Revised September 13, 2001




GVT71256T18 pdf, 반도체, 판매, 대치품
CY7C1359A/GVT71256T18
Pin Descriptions
BGA Pins
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
2T, 3T, 5T, 6T
5L
3G
4M
4H
4K
4E
6B
2B
4F
4G
4A
4B
3R
7T
7N
6M
TQFP Pins
37
36
35, 34, 33, 32,
100, 99, 82, 81,
80, 48, 47, 46, 45,
44, 49, 50
93
94
87
88
89
98
92
97
86
83
84
85
31
64
52
53
Name
A0
A1
A
Type
Input-
Synchronous
Description
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The
burst counter generates internal addresses associated with
A0 and A1, during burst cycle and wait cycle.
WEL
WEH
Input-
Synchronous
Byte Write Enables: A byte write enable is LOW for a WRITE
cycle and HIGH for a READ cycle. WEL controls DQ1DQ9.
WEH controls DQ10DQ18. Data I/O are high impedance if
either of these inputs are LOW, conditioned by BWE being
LOW.
BWE
Input-
Write Enable: This active LOW input gates byte write opera-
Synchronous tions and must meet the set-up and hold times around the
rising edge of CLK.
GW
Input-
Global Write: This active LOW input allows a full 18-bit
Synchronous WRITE to occur independent of the BWE and WEn lines and
must meet the set-up and hold times around the rising edge
of CLK.
CLK
Input-
Clock: This signal registers the addresses, data, chip en-
Synchronous ables, write control, and data input enable control input on its
rising edge. All synchronous inputs must meet set-up and
hold times around the clocks rising edge.
CE
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device and to gate ADSP.
CE2
Input-
Chip Enable: This active LOW input is used to enable the
Synchronous device.
CE2
input-
Chip Enable: This active HIGH input is used to enable the
Synchronous device.
OE
Input
Output Enable: This active LOW asynchronous input enables
the data output drivers.
ADV
Input-
Address Advance: This active LOW input is used to control
Synchronous the internal burst counter. A HIGH on this pin generates wait
cycle (no address advance).
ADSP
Input-
Address Status Processor: This active LOW input, along with
Synchronous CE being LOW, causes a new external address to be regis-
tered and a READ cycle is initiated using the new address.
ADSC
Input-
Synchronous
Address Status Controller: This active LOW input causes de-
vice to be deselected or selected along with new external
address to be registered. A READ or WRITE cycle is initiated
depending upon write control inputs.
MODE
Input-
Static
Mode: This input selects the burst sequence. A LOW on this
pin selects Linear Burst. A NC or HIGH on this pin selects
Interleaved Burst.
ZZ
Input-
Snooze: This active HIGH input puts the device in low power
Asynchronous consumption standby mode. For normal operation, this input
has to be either LOW or NC (No Connect).
DEN
Input-
Data Input Enable: This active LOW input is used to control
Synchronous the update of data input registers.
MATCH
Output
Match Output: MATCH will be HIGH if data in the data input
registers match the data stored in the memory array, assum-
ing MOE being LOW. MATCH will be LOW if data do not
match.
Document #: 38-05120 Rev. **
Page 4 of 24

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GVT71256T18 전자부품, 판매, 대치품
CY7C1359A/GVT71256T18
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modi-
fied or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Stan-
dard 1149.1 compliant TAPs. The TAP operates using
LVTTL/LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI - Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruc-
tion that is currently loaded in the TAP instruction register (re-
fer to Figure 1, TAP Controller State Diagram). It is allowable
to leave this pin unconnected if it is not used in an application.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI is connected to the most significant bit (MSB) of any reg-
ister. (See Figure 2.)
TDO - Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1, TAP Controller State
Diagram). Output changes in response to the falling edge of
TCK. This is the output side of the serial registers placed be-
tween TDI and TDO. TDO is connected to the least significant
bit (LSB) of any register. (See Figure 2.)
Performing a TAP Reset
The TAP circuitry does not have a Reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction reg-
ister with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are execut-
ed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruc-
tion upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Cap-
ture-IR state, the two least significant bits of the serial instruc-
tion register are loaded with a binary 01pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for a x36 device and
51 bits for a x18 device. The boundary scan register, under the
control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the con-
troller is moved to Shift-DR state. The EXTEST, SAMPLE/
PRELOAD and SAMPLE-Z instructions can be used to cap-
ture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bits posi-
tion in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name and the third column is the bump
number. The third column is the TQFP pin number and the
fourth column is the BGA bump number.
Document #: 38-05120 Rev. **
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GVT71256T18

(GVT71256T18 / GVT7C1359A) 256K X 18 Synchronous-pipelined Cache Tag RAM

Cypress Semiconductor
Cypress Semiconductor

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