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PDF MRFIC1806 Data sheet ( Hoja de datos )
| Número de pieza | MRFIC1806 | |
| Descripción | 1.8 GHz DRIVER AMPLIFIER AND RAMP CIRCUIT GaAs MONOLITHIC INTEGRATED CIRCUIT | |
| Fabricantes | Motorola Semiconductors | |
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( DataSheet : www.DataSheet4U.com )
MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
The MRFIC Line
1.8 GHz PA Driver/Ramp
Designed primarily for use in DECT, Japan Personal Handy System (PHS),
and other wireless Personal Communication Systems (PCS) applications. The
MRFIC1806 includes a two stage driver amplifier and transmit waveform
shaping circuitry in a low–cost SOIC–16 package. The amplifier portion
employs depletion mode power GaAs MESFETs to produce +21 dBm output
with 0 dBm input. The ramping circuit controls the burst–mode transmit rise and
fall time and is adjustable through external components. This circuitry also
places the amplifier in standby during TDMA receive mode. The MRFIC1806 is
sized to drive the MRFIC1807 PA/Switch.
Together with the rest of the MRFIC1800 GaAs ICs, this family offers the
complete transmit and receive functions, less LO and filters, needed for a
typical 1.8 GHz cordless telephone.
• Usable 1500 – 2500 MHz
• 23 dB Typical Gain
• +21 dBm Typical 1.0 dB Compression
• Simple Off–Chip Matching for Maximum Flexibility
• 3.0 to 5.0 Volt Supply
• Low Cost Surface Mount Plastic Package
• Order MRFIC1806R2 for Tape and Reel.
R2 Suffix = 2,500 Units per 16 mm, 13 inch Reel.
• Device Marking = M1806
Order this document
by MRFIC1806/D
MRFIC1806
1.8 GHz DRIVER AMPLIFIER
AND RAMP CIRCUIT
GaAs MONOLITHIC
INTEGRATED CIRCUIT
CASE 751B–05
(SO–16)
C1/VRAMP 1
TX RAMP 2
REG VDD 3
GND 4
GND 5
RF IN 6
VDD 7
PCNTRL 8
20K
LOGIC
XLATOR
RAMP
VSS VDD
GATE
BIAS
16 VDR
15 GND
14 VD1
13 GND
12 GND
11 RF OUT
10 GND
9 VSS
Figure 1. Pin Connections and Functional Block Diagram
REV 2
MOTOROLA
www©.DaMtoatSorhoelae, tI4nUc..1c9o9m7
www.DataSheet4U.com
MRFIC1806
1
1 page  
DESIGN AND APPLICATIONS INFORMATION
DESIGN PHILOSOPHY
The MRFIC1806 is designed to drive the MRFIC1807
Power Amplifier and Transmit/Receive Switch IC in Personal
Communications System (PCS) applications such as
Europe’s DECT and Japan’s Personal Handy System (PHS).
The design incorporates not only a two–stage GaAs MESFET
driver/exciter amplifier, but also externally controllable bias
and ramping circuitry. The IC is designed to drive the
MRFIC1807 with about +19 dBm which will, in turn, produce
+26 dBm output, suitable for DECT. To reduce chip size (and
cost) and to allow for flexibility of application, the amplifier
has limited on–chip matching. The ramp circuitry is used to
shape the drain voltage to the FETs for Time Domain Multiple
Access (TDMA) applications and is comprised of a depletion
mode pass device driven by a logic translator. Attack and
release times are controllable through the use of external
components. The IC is configured such that all, part or none
of the ramping circuitry can be used, depending on the
application.
AMPLIFIER CIRCUIT APPLICATION
As can be seen in Figures 2 and 3, the off–chip matching is
straight forward. At frequencies near 1.9 GHz, the input
requires 4.7 nH in series and 1.5 pF in shunt. The 4.7 nH
series inductance may be implemented with a high–
impedance transmission line as shown. The output, being
close to 25 Ω, requires only a shunt 1.5 pF capacitor. Drain
voltage for stage 1 is supplied through pin 14 and for stage 2
through pin 11, the RF output. Pin 8, PCNTRL is used to set
the quiescent bias point for both stages. While nominal IDDQ
is 120 mA, it can be set as high as 180 mA for better linearity
or lower for better efficiency. 120 mA is a good compromise
for DECT and PHS. DECT, which employs GMSK constant
envelope modulation can use RF amplifiers close to or in
saturation without experiencing spectral regrowth of the
signal. PHS, on the other hand, employs π/4 DQPSK
modulation which has some residual AM associated with the
encoding. With AM present, RF amplifiers must be backed
off from saturation so as not to regrow the filtered sidebands.
The MRFIC1806 has plenty of backoff capability for PHS
where the MRFIC1807 PA/switch must only produce about
+21 dBm. With the 8.0 dB gain of the MRFIC1807, the
MRFIC1806 need only produce +13 dBm output so the bias
point can be reduced below the 120 mA suggested for DECT.
As with all RF circuits, board layout and grounding are
important. All RF signal paths must be controlled impedance
structures. RF chip components must be high quality.
Bypassing capacitors must be close to the IC and to ground
vias. Pins which are designated as ground connections must
be as close as possible to ground vias.
RAMPING CIRCUIT OPTIONS
The on–chip ramp circuit can be used to control the
amplifier attack and release time for DECT applications
through the use of a few external components as shown in
Figure 2. This ramping is required to control the burst signal
rise and fall time to avoid adjacent channel interference. At
the same time, system specifications require the transmitter
to reach full power in a minimum time. For DECT, it has been
shown that a rise time of not greater than 2 microseconds will
produce acceptable adjacent channel performance. The
system requires full power in not greater than 10 microseconds.
A good compromise, and the timing implemented in Figure 2,
is 7 microseconds.
The on–chip logic translator can be bypassed as shown in
Figure 3 by applying a ramp voltage to Pin 1 through a 1.0 kΩ
resistor. This configuration allows flexibility in ramping the
amplifier. The regulated VDD voltage is not required so
current consumption can be reduced. – 2.3 V at Pin 1 turns
the pass transistor, and the amplifier, off while a positive
voltage will turn the pass transistor on. For full on state it is
recommended that VRAMP be close to VDD. VRAMP can also
be used to on–off key the amplifier for simple telemetry
applications or as transmit/receive control.
For more complex modulation schemes such as π/4
DQPSK used in PHS, burst ramping can be implemented
with the burst mode logic. Referring to Figure 3, the VRAMP
voltage should be set to VDD to leave the pass transistor on.
The on–chip pass transistor can also be bypassed and VDD
applied to Pins 11 and 14.
EVALUATION BOARDS
Evaluation boards are available for RF Monolithic
Integrated Circuits by adding a “TF” suffix to the device
type. For a complete list of currently available boards and
ones in development for newly introduced product, please
contact your local Motorola Distributor or Sales Office.
MOTOROLA
MRFIC1806
5
5 Page 
PACKAGE DIMENSIONS
–A–
16
1
9
–B– P 8 PL
8 0.25 (0.010) M B S
G
–T– SEATING
PLANE
K
C
D 16 PL
0.25 (0.010) M T B S A S
R X 45_
F
MJ
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
MILLIMETERS
INCHES
DIM MIN MAX MIN MAX
A 9.80 10.00 0.386 0.393
B 3.80 4.00 0.150 0.157
C 1.35 1.75 0.054 0.068
D 0.35 0.49 0.014 0.019
F 0.40 1.25 0.016 0.049
G 1.27 BSC
0.050 BSC
J 0.19 0.25 0.008 0.009
K 0.10 0.25 0.004 0.009
M 0_ 7_ 0_ 7_
P 5.80 6.20 0.229 0.244
R 0.25 0.50 0.010 0.019
CASE 751B–05
ISSUE J
MOTOROLA
MRFIC1806
11
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet MRFIC1806.PDF ] | |
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