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P8M644YL 데이터시트 PDF




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부품번호 P8M644YL 기능
기능 (P8M644YL / P8M648YL) 4M/8M x 64 DIMM SDRAM Module
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P8M644YL 데이터시트, 핀배열, 회로
SDRAM MODULE
Features:
JEDEC - Standard 168-pin (gold), dual in-line memory
module (DIMM).
TSOP components.
Single 3.3v +.3v power supply.
Nonbuffered fully synchronous; all signals measured on
positive edge of system clock.
Internal pipelined operation; column address can be
changed every clock cycle.
Quad internal banks for hiding row access/precharge.
64ms 4096 cycle refresh.
All inputs, outputs, clocks LVTTL compatible.
Options:
4 - 4Mx16 SDRAM TSOP
8 - 4Mx16 SDRAM TSOP
Part Number:
P4M644YL-XX
P8M648YL-XX
KEY DIMM MODULE TIMING PARAMETERS
Module
Component Clock CAS Latency
Marking Marking
Freq
-66CL2
-10/-12
66MHZ
2 or 3
-100CL3A -8A
100MHZ
3
GENERAL DESCRIPTION
The S4M644YL and S8M648YL are high performance
dynamic random-access 32MB and 64MB modules
respectively. These modules are organized in a x64
configuration, and utilize dual bank architecture with a
synchronous interface. All signals are registered on the
positive edge of the clock signals CK0 through CK3. Read and
write accesses to the SDRAM are burst oriented; accesses
start at a location and continue for a programmed number of
locations in a sequence. Accesses begin with an ACTIVE
command, which is followed by a READ or WRITE command.
ABSOLUTE MAXIMUM RATINGS:
Voltage on Vcc Supply relative to Vss...................-1 to +4.6V
Operating Temperature TA (Ambient) .............25 ° to +70 °C
Storage Temperature ......................................-55 to +125 °C
Power Dissipation……………………………………4 or 8 W
Short Circuit Output Current……………………….….50 mA
Stresses beyond these may cause permanent damage to the
device. This is a stress rating only and functional operation
of the device at or beyond these conditions is not implied.
Exposure to these conditions for extended periods may affect
reliability.
P4M644YL, P8M648YL
4M, 8M x 64 DIMM
PIN ASSIGNMENT (Front View)
168-PIN DIMM
Pin Name Pin Name
1 Vss 43 Vss
2
DQ0
44
DU
3 DQ1 45 S2#
4
DQ2
46 DQMB2
5
DQ3
47 DQMB3
6
Vcc 48
DU
7
DQ4
49
Vcc
8
DQ5
50
NC
9
DQ6
51
NC
10 DQ7 52
NC
11 DQ8 53
NC
12 Vss 54 Vss
13 DQ9 55 DQ16
14
DQ10
56
DQ17
15
DQ11
57
DQ18
16
DQ12
58
DQ19
17
DQ13
59
Vcc
18 Vcc 60 DQ20
19
DQ14
61
NC
20
DQ15
62
NC
21 NC 63 CKE1
22 NC 64 Vss
23 Vss 65 DQ21
24 NC 66 DQ22
25 NC 67 DQ23
26 Vcc 68 Vss
27 WE# 69 DQ24
28 DQMB0 70
DQ25
29 QQMB1 71
DQ26
30 SO# 72 DQ27
31 DU 73 Vcc
32 Vss 74 DQ28
33 A0 75 DQ29
34 A2 76 DQ30
35 A4 77 DQ31
36 A6 78 Vss
37 A8 79 CK2
38 A10/AP 80
NC
39 BA1 81 NC
40 Vcc 82 SDA
41 Vcc 83 SCL
42 CK0 84 Vcc
Pin Name Pin Name
85 Vss 127 Vss
86 DQ32 128 CKE0
87
DQ33
129
S3#
88
DQ34
130 DQMB6
89
DQ35
131 DQMB7
90 Vcc 132 RFU
91
DQ36
133
Vcc
92
DQ37
134
NC
93
DQ38
135
NC
94
DQ39
136
NC
95
DQ40
137
NC
96 Vss 138 Vss
97 DQ41 139 DQ48
98 DQ42 140 DQ49
99 DQ43 141 DQ50
100 DQ44 142 DQ51
101 DQ45 143
Vcc
102 Vcc 144 DQ52
103 DQ46 145
NC
104 DQ47 146
NC
105 NC 147 NC
106 NC 148 Vss
107 Vss 149 DQ53
108 NC 150 DQ54
109 NC 151 DQ55
110 Vcc 152 Vss
111 CAS# 153 DQ56
112 DQMB4 154
DQ57
113 DQMB5 155
DQ58
114 S1# 156 DQ59
115 RAS# 157
Vcc
116 Vss 158 DQ60
117 A1 159 DQ61
118 A3 160 DQ62
119 A5 161 DQ63
120 A7 162 Vss
121 A9 163 CK3
122 BA0 164 NC
123 A11 165 SA0
124 Vcc 166 SA1
125 CK1 167 SA2
126 RFU 168 Vcc
__________________________________________________________________________________________________
P4M644
1 SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. ©1999 SpecTek




P8M644YL pdf, 반도체, 판매, 대치품
P4M644YL, P8M648YL
SERIAL PRESENCE-DETECT OPERATION - This module incorporates Serial Presence-Detect (SPD) . The SPD function is
implemented using a 2,048 bit EEPROM, containing 256 bytes of nonvolatile storage. The first 128 bytes can be programmed by
SpecTek to identify the module type and various DRAM organization and timing parameters. The remaining 128 bytes of storage are
available for use by the customer. System READ/WRITE operations between the master (system logic) and the slave EEPROM device
(DIMM) occur via a standard IIC bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA(2:0), which provide 8
unique DIMM/EEPROM addresses.
SPD CLOCK AND DATA CONVENTIONS - Data states on the SDA line can change only during SCL LOW. SDA state changes during
SCL HIGH are reserved for indicating start and stop conditions (Figures 1 and 2).
SPD START CONDITION - All commands are preceded by the start condition, which is a HIGH to LOW transition of SDA when SCL is
HIGH. The serial PD device continuously monitors the SDA and SCL lines for the start condition and will not respond to any command
until this condition has been met.
SPD STOP CONDITION - All communications are terminated by a stop condition, which is a LOW to HIGH transition of SDA when SCL
is HIGH. The stop condition also places the serial PD device into standby power mode.
SPD ACKNOWLEDGE - Acknowledge is a software convention used to indicate successful data transfers. The transmitting device,
either master or slave, will release the bus after transmitting eight bits of data (Figure 3).
The PD device will always respond with an acknowledge after recognition of a start condition and its slave address. If both the
device and a write operation have been selected, the PD device will respond with an acknowledge after the receipt of each subsequent
eight bit word. In the read mode the PD device will transmit eight bits of data, release the SDA line and monitor the line for an
acknowledge. If an acknowledge is not detected, the slave will terminate further data transmissions and await the stop condition to return
to standby power mode.
SERIAL PRESENCE-DETECT EEPROM DC OPERATING CONDITIONS (VCC = +3.3V m 0.3V)
PARAMETER/CONDITION
Symbol
MIN
MAX
Units
Supply Voltage
Input High (Logic 1) Voltage, all inputs
Input Low (Logic 0) Voltage, all inputs
OUTPUT LOW VOLTAGE, IOUT =3mA
INPUT LEAKAGE CURRENT, VIN = GND to Vcc
VCC 3.0 3.6 V
VIH Vcc x .7 Vcc x .5 V
VIL -1.0 Vcc x .3 V
VOL 0.4 V
ILI 10 µA
OUTPUT LEAKAGE CURRENT, VOUT = GND to Vcc ILO 10 µA
STANDBY CURRENT SCL=SDA=Vcc -0.3V, All other inputs = GND
or 3.3V +10%
ISB
30 µA
POWER SUPPLY CURRENT SCL clock frequency = 100 KHz
ICC
2 µA
Notes
SERIAL PRESENCE-DETECT EEPROM AC OPERATING CONDITIONS (VCC = +3.3V m 0.3V)
AC CHARACTERISTICS
PARAMETER/CONDITION
SCL LOW to SDA data-out valid
IIdle bus time before a transition can start
Data-out hold time
SDA and SCL fall time
Data-in hold time
Start condition hold time
Clock HIGH period
Noise suppresssion time constant at SCL, SDA inputs
Clock LOW period
SDA and SCL rise time
SCL clock frequency
Data-in setup time
Start condition setup time
Stop condition setup time
WRITE cycle time
Symbol
tAA
tBUF
tDH
tF
THD:DAT
THD:STA
tHIGH
tl
tLOW
tR
tSCL
TSU:DAT
TSU:STA
TSU:STO
tW R
MIN
0.3
4.7
300
0
4
4
4.7
250
4.7
4.7
MAX
3.5
300
100
1
100
10
Units
µs
µs
ns
ns
µs
µs
µs
ns
µs
µs
KHz
ns
µs
µs
ms
Notes
1
NOTES:
1. The SPD EEPROM WRITE cycle time (tWR) is the time from a valid stop condition of a WRITE sequence to the end of the
EEPROM internal erase/program cycle. During the WRITE cycle the EEPROM bus interface circuit is disabled, SDA remains HIGH due
to pull-up resistor, and the EEPROM does not respond to its slave address.
__________________________________________________________________________________________________
P4M644
4 SpecTek reserves the right to change products
Rev: 6/14/99
or specifications without notice. ©1999 SpecTek

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