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부품번호 | 16C550 기능 |
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기능 | TL16C550 | ||
제조업체 | ETC | ||
로고 | |||
전체 30 페이지수
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
D Capable of Running With All Existing
TL16C450 Software
D After Reset, All Registers Are Identical to
the TL16C450 Register Set
D In the FIFO Mode, Transmitter and Receiver
Are Each Buffered With 16-Byte FIFOs to
Reduce the Number of Interrupts to the
CPU
D In the TL16C450 Mode, Holding and Shift
Registers Eliminate the Need for Precise
Synchronization Between the CPU and
www.DataSheet4U.com Serial Data
D Programmable Baud Rate Generator Allows
Division of Any Input Reference Clock by 1
to (216 – 1) and Generates an Internal 16×
Clock
D Standard Asynchronous Communication
Bits (Start, Stop, and Parity) Added to or
Deleted From the Serial Data Stream
D Independent Receiver Clock Input
D Transmit, Receive, Line Status, and Data
Set Interrupts Independently Controlled
D Fully Programmable Serial Interface
Characteristics:
– 5-, 6-, 7-, or 8-Bit Characters
– Even-, Odd-, or No-Parity Bit Generation
and Detection
– 1-, 1 1/2-, or 2-Stop Bit Generation
– Baud Generation (dc to 256 Kbit/s)
D False-Start Bit Detection
D Complete Status Reporting Capabilities
D 3-State TTL Drive Capabilities for
Bidirectional Data Bus and Control Bus
D Line Break Generation and Detection
D Internal Diagnostic Capabilities:
– Loopback Controls for Communications
Link Fault Isolation
– Break, Parity, Overrun, Framing Error
Simulation
D Fully Prioritized Interrupt System Controls
D Modem Control Functions (CTS, RTS, DSR,
DTR, RI, and DCD)
D Faster Plug-In Replacement for National
Semiconductor NS16550A
description
The TL16C550A is a functional upgrade of the TL16C450 asynchronous communications element (ACE).
Functionally identical to the TL16C450 on power up (character mode†), the TL16C550A can be placed in an
alternate mode (FIFO) to relieve the CPU of excessive software overhead.
In this mode, internal FIFOs are activated allowing 16 bytes (plus 3 bits of error data per byte in the receiver
FIFO) to be stored in both receive and transmit modes. To minimize system overhead and maximize system
efficiency, all logic is on the chip. Two of the TL16C450 terminal functions (terminals 24 and 29 on the N package
and terminals 27 and 32 on the FN package) have been changed to allow signalling of direct memory address
(DMA) transfers.
The TL16C550A performs serial-to-parallel conversion on data received from a peripheral device or modem
and parallel-to-serial conversion on data received from its CPU. The CPU can read and report on the status of
the ACE at any point in the ACE’s operation. Reported status information includes the type of transfer operation
in progress, the status of the operation, and any error conditions encountered.
The TL16C550A ACE includes a programmable, on-board, baud rate generator. This generator is capable of
dividing a reference clock input by divisors from 1 to (216 – 1) and producing a 16 × clock for driving the internal
transmitter logic. Provisions are included to use this 16× clock to drive the receiver logic. Also included in the
ACE is a complete modem control capability and a processor interrupt system that may be software tailored
to the user’s requirements to minimize the computing required to handle the communications link.
† The TL16C550A can also be reset to the TL16C450 mode under software control.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 1996, Texas Instruments Incorporated
1
TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
Terminal Functions
TERMINAL
NAME
NO.† I/O
DESCRIPTION
A0 28 [31] I Register select. A0, A1, and A2 are used during read and write operations to select the ACE register to read from
A1
27 [30]
or write to. Refer to Table 1 for register addresses, also refer to the address strobe (ADS) signal description.
A2 26 [29]
ADS
25 [28] I Address strobe. When ADS is active (low), the register select signals (A0, A1, and A2) and chip select signals (CS0,
CS1, CS2) drive the internal select logic directly; when high, the register select and chip select signals are held in
the state they were in when the low-to-high transition of ADS occurred.
BAUDOUT 15 [17] O Baud out. BAUDOUT is a 16 × clock signal for the transmitter section of the ACE. The clock rate is established by
the reference oscillator frequency divided by a divisor specified by the baud generator divisor latches. BAUDOUT
may also be used for the receiver section by tying this output to the RCLK input.
www.DataSheCeSt40U.com 12 [14] I Chip select. When CSx is active (high, high, and low respectively), the ACE is selected. If any of these inputs are
CS1
13 [15]
inactive, the ACE remains inactive. Refer to the ADS (address strobe) signal description.
CS2 14 [16]
CTS
36 [40] I Clear to send. CTS is a modem status signal. Its condition can be checked by reading bit 4 (CTS) of the modem
status register. Bit 0 (DCTS) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when CTS changes state, an
interrupt is generated.
D0 – D7
1 – 8 I/O Data bus. Eight 3-state data lines provide a bidirectional path for data, control, and status information between the
[2 – 9]
ACE and the CPU.
DCD
38 [42] I Data carrier detect. DCD is a modem status signal. Its condition can be checked by reading bit 7 (DCD) of the
modem status register. Bit 3 (DDCD) of the modem status register indicates that this signal has changed states
since the last read from the modem status register. If the modem status interrupt is enabled when the DCD changes
state, an interrupt is generated.
DDIS
23 [26] O Driver disable. This output is active (high) when the CPU is not reading data. When active, this output can disable
an external transceiver.
DSR
37 [41] I Data set ready. DSR is a modem status signal. Its condition can be checked by reading bit 5 (DSR) of the modem
status register. Bit 1 (DDSR) of the modem status register indicates that this signal has changed states since the
last read from the modem status register. If the modem status interrupt is enabled when the DSR changes state,
an interrupt is generated.
DTR
33 [37] O Data terminal ready. When active (low), DTR informs a modem or data set that the ACE is ready to establish
communication. DTR is placed in the active state by setting the DTR bit of the modem control register to a high level.
DTR is placed in the inactive state either as a result of a master reset or during loop mode operation or clearing
bit 0 (DTR) of the modem control register.
INTRPT
30 [33] O Interrupt. When active (high), INTRPT informs the CPU that the ACE has an interrupt to be serviced. Four
conditions that cause an interrupt to be issued are: a receiver error, received data is available or timeout (FIFO mode
only), transmitter holding register empty, or an enabled modem status interrupt. The INTRPT output is reset
(deactivated) either when the interrupt is serviced or as a result of a master reset.
MR 35 [39] I Master reset. When active (high), MR clears most ACE registers and sets the state of various output signals. Refer
to Table 2.
OUT1
OUT2
34 [38] O Outputs 1 and 2. OUT1 and OUT2 are user-designated output terminals that are set to their active states by setting
31 [35]
their respective modem control register bits (OUT1 and OUT2) high. OUT1 and OUT2 are set to their inactive (high)
states as a result of master reset or during loop mode operations or by clearing bit 2 (OUT1) or bit 3 (OUT2) of the
modem control register.
RCLK
9 [10] I Receiver clock. RCLK is the 16× baud rate clock for the receiver section of the ACE.
RD1
21 [24] I Read inputs. When either RD1 or RD2 are active (high or low respectively) while the ACE is selected, the CPU is
RD2
22 [25]
allowed to read status information or data from a selected ACE register. Only one of these inputs is required for
the transfer of data during a read operation; the other input should be tied in its inactive state (i.e., RD2 tied low
or RD1 tied high).
† Terminal numbers shown in brackets are for the FN package.
•4 POST OFFICE BOX 655303 DALLAS, TEXAS 75265
4페이지 TL16C550A
ASYNCHRONOUS COMMUNICATIONS ELEMENT
SLLS057D – AUGUST 1989 – REVISED MARCH 1996
system timing requirements over recommended ranges of supply voltage and operating free-air
temperature
tcR Cycle time, read (tw7 + td8 + td9)
tcW Cycle time, write (tw6 + td5 + td6)
tw5 Pulse duration, ADS low
tw6 Pulse duration, write strobe
tw7 Pulse duration, read strobe
tw8 Pulse duration, master reset
tsu1 Setup time, address valid before ADS ↑
tsu2 Setup time, CS before ADS ↑
tsu3
www.DataSheet4U.tcho1m
Setup time, data valid before WR1 ↓ or WR2 ↑
Hold time, address low after ADS ↑
th2 Hold time, CS valid after ADS ↑
th3 Hold time, CS valid after WR1 ↑ or WR2 ↓
th4§ Hold time, address valid after WR1 ↑ or WR2 ↓
th5 Hold time, data valid after WR1 ↑ or WR2 ↓
th6 Hold time, CS valid after RD1↑ or RD2↓
th7§ Hold time, address valid after RD1↑ or RD2↓
td4§ Delay time, CS valid before WR1 ↓ or WR2 ↑
td5§ Delay time, address valid before WR1 ↓ or WR2 ↑
td6§ Delay time, write cycle, WR1 ↑ or WR2 ↓ to ADS ↓
td7§
Delay time, CS valid to RD1↓ or RD2 ↑
td8§ Delay time, address valid to RD1↓ or RD2↑
td9 Delay time, read cycle, RD1↑ or RD2↓ to ADS↓
§ Applicable only when ADS is tied low.
ALT. SYMBOL
RC
WC
tADS
tWR
tRD
tMR
tAS
tCS
tDS
tAH
tCH
tWCS
tWA
tDH
tRCS
tRA
tCSW
tAW
tWC
tCSR
tAR
tRC
FIGURE
2, 3
2
3
2, 3
2, 3
2
2, 3
2, 3
2
2
2
3
3
2
2
2
3
3
3
MIN MAX UNIT
175 ns
175 ns
15 ns
80 ns
80 ns
1 µs
15 ns
15 ns
15 ns
0 ns
0 ns
20 ns
20 ns
15 ns
20 ns
20 ns
15 ns
15 ns
80 ns
15 ns
15 ns
80 ns
system switching characteristics over recommended ranges of supply voltage and operating
free-air temperature (see Note 2)
PARAMETER
ALT. SYMBOL FIGURE
tw1 Pulse duration, clock high
tXH 1
tw2 Pulse duration, clock low
tXL 1
td10 Delay time, RD1↓ or RD2↑ to data valid
tRVD
3
td11 Delay time, RD1↑ or RD2↓ to floating data
tHZ
3
tdis(R) Disable time, RD1↓↑ or RD2↑↓ to DDIS↑↓
tRDD
3
NOTE 2: Charge and discharge time is determined by VOL, VOH, and external loading.
TEST CONDITIONS
f = 9 MHz maximum
f = 9 MHz maximum
CL = 100 pF
CL = 100 pF
CL = 100 pF
MIN MAX UNIT
50 ns
50 ns
60 ns
0 60 ns
60 ns
baud generator switching characteristics over recommended ranges of supply voltage and
operating free-air temperature
PARAMETER
tw3 Pulse duration, BAUDOUT low
tw4 Pulse duration, BAUDOUT high
td1 Delay time, XIN ↑ to BAUDOUT ↑
td2 Delay time, XIN ↑↓ to BAUDOUT ↓
ALT. SYMBOL
tLW
FIGURE
1
tHW
tBLD
tBHD
1
1
1
TEST CONDITIONS
f = 9 MHz, CLK ÷ 2,
CL = 100 pF
f = 9 MHz, CLK ÷ 2,
CL = 100 pF
CL = 100 pF
CL = 100 pF
MIN MAX UNIT
80 ns
100 ns
125 ns
125 ns
•POST OFFICE BOX 655303 DALLAS, TEXAS 75265
7
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부품번호 | 상세설명 및 기능 | 제조사 |
16C550 | TL16C550 | ETC |
16C552 | Dual FIFO UART and Parallel Port | IMP Inc |
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