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PDF DD-00429 Data sheet ( Hoja de datos )
| Número de pieza | DD-00429 | |
| Descripción | ARINC 429 Microprocessor Interface | |
| Fabricantes | Data Device Corporation | |
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DD-00429
ARINC 429 MICROPROCESSOR
INTERFACE
DESCRIPTION
DDC's DD-00429 provides a complete and flexible interface between
a microprocessor and an ARINC 429 data bus. The DD-00429 inter-
faces to a processor through a 128 x 32 bit static ram as well as four
32 x 32 receive FIFOs and two 32 x 32 transmit FIFOs. The DD-
00429 can be easily interfaced to 8- or 16-bit processors via a
buffered shared RAM configuration.
The DD-00429, when configured with two Transceivers, supports four
ARINC 429 Receive channels (Rx0, Rx1, Rx2 and Rx3) each receiv-
ing data independently. The receive data rates (high or low speed) for
channel Rx0 and Rx1 can be programmed independently from Rx2
and Rx3. The DD-00429 can decode and sort data based on the
ARINC 429 Label and SDI bits via the Data Match Processor, and
store it in RAM and/or FIFOs via the Data Store Processor.
The DD-00429, when configured with two Line Drivers, supports two
ARINC 429 Transmit channels (Tx0 and Tx1) and can transmit data
independently. The transmit data rate can also be programmed inde-
pendently. There are two 32 x 32 bit FIFOs for each of the transmit-
ters that send out data.
The DD-00429 has the capability of programming three general pur-
pose interrupts as well as generating an interrupt based on an error
condition. The general purpose interrupts can be programmed to trig-
ger other external hardware. They can either be LEVEL or PULSE
driven.
The features built into the DD-00429 enable the user to off-load the
host processor and use that processing time to implement operations
other than polling the ARINC 429 Bus. The decoding and sorting of
data allows the user to gather data much quicker than past designs.
If the user requires a microprocessor in the avionics box, this device
will facilitate a clean and quick design.
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
Make sure the next
Card you purchase
has...
®
FEATURES
• Four ARINC 429 Receive Channels,
(configured with Transceivers)
• Two ARINC 429 Transmit Channels
(configured with Drivers)
• 128 x 32 Shared RAM Interface
• Label and Destination Decoding and
Sorting
• Two 32 x 32 Transmit FIFO's
• Four 32 x 32 Receive FIFO’s
• Interfaces Easily to 8- or 16-Bit
Microprocessor
• Built-in Fault Detection Circuitry
• Free “C” Library Software
• Application Note AN/A-6 “FAQ’s”
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7234
All trademarks are the property of their respective owners.
© 1998, 1999 Data Device Corporation
1 page  
PROCESSOR INTERFACE
The processor interface allows for the use of either an 8- or 16-
bit data bus. Intel or Motorola control signal formats can also be
used.
INTERRUPT OPERATIONAL MODES
The DD-00429 provides four interrupt outputs. Three of these
interrupt outputs (IRQ1, IRQ2, and IRQ3) are general purpose
programmable interrupts. The fourth interrupt is an Error interrupt
output which is specifically used to provide indications of various
error conditions and is nonmaskable.
ERROR INTERRUPT OPERATION
When an error condition occurs, the ERROR output pin goes low
to indicate the presence of an error. The error pin will go high
again when the Error Status Register is clear. Each of these bits
is cleared by either reading the Error Status Register or remov-
ing the error condition.
GENERAL PURPOSE INTERRUPTS
The three general purpose interrupt outputs can be used for mul-
tilevel interrupts or to trigger other external hardware for various
conditions. Each condition can be mapped to any one of the
three general purpose interrupts or disabled (by mapping to
IRQ0 which does not exist). Each interrupt output can be pro-
grammed to be either a LEVEL interrupt or PULSE interrupt via
the associated IRQ Control Register 2. When programmed for
pulse interrupt mode, the associated interrupt pin will go low for
1 µS and return high again. When programmed for LEVEL inter-
rupt mode, the interrupt will remain until the associated IRQ
Status Register is read, thus clearing the associated bits in each
interrupt register.
Each of the individual interrupt registers can be masked by set-
ting their corresponding bit in IRQ Control Register 1. It should
be noted that the masking function only prevents the associated
IRQ pin from becoming active. When the mask bit is cleared, an
interrupt can occur in LEVEL IRQ mode if one or more interrupt
conditions occurred during the time when the mask was set. If
the user needs to ensure the interrupt will not occur upon clear-
ing the mask bit, the CPU should be programmed to read the
associated interrupt status register immediately prior to clearing
the IRQ mask bit.
ZERO WAIT MODE OPERATION
When Zero Wait Mode is enabled by not grounding the ZERO
WAIT pin, the host microprocessor may read data from the DD-
00429 shared memory resources (DMT and Rx RAM) without
using the READY or DTACK signals to insert wait states into the
microprocessor cycle. This is accomplished by an additional
“dummy read” of the desired address. This dummy read causes
the DD-00429 to fetch the data from the source and place it in a
latch. The data can then be read from the latch (word-by-word or
byte-by-byte) by reading the same addresses. Thus for a 32-bit
read in 8-bit mode, the microprocessor would perform a total of
five read operations. The first read would be the dummy read;
subsequent reads would transfer the data.
Data Device Corporation
www.ddc-web.com
5
DD-00429
G1 web-09/02-0
5 Page | ||
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| PDF Descargar | [ Datasheet DD-00429.PDF ] | |
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