PC74HCT4353 Datasheet PDF - NXP Semiconductors
| Part Number | PC74HCT4353 | |
| Description | Triple 2-Channel Analog Multiplexer / Demultiplexer | |
| Manufacturers | NXP Semiconductors | |
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74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
Rev. 8 — 19 July 2012
Product data sheet
1. General description
The 74HC4053; 74HCT4053 is a high-speed Si-gate CMOS device and is pin compatible
with the HEF4053B. It is specified in compliance with JEDEC standard no. 7A.
The 74HC4053; 74HCT4053 is triple 2-channel analog multiplexer/demultiplexer with a
common enable input (E). Each multiplexer/demultiplexer has two independent
inputs/outputs (nY0 and nY1), a common input/output (nZ) and three digital select
inputs (Sn). With E LOW, one of the two switches is selected (low-impedance ON-state)
by S1 to S3. With E HIGH, all switches are in the high-impedance OFF-state, independent
of S1 to S3.
VCC and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The VCC to GND ranges are 2.0 V to 10.0 V for 74HC4053 and 4.5 V to 5.5 V for
74HCT4053. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between VCC as
a positive limit and VEE as a negative limit. VCC VEE may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, VEE is connected to GND (typically
ground).
2. Features and benefits
Wide analog input voltage range from 5 V to +5 V
Low ON resistance:
80 (typical) at VCC VEE = 4.5 V
70 (typical) at VCC VEE = 6.0 V
60 (typical) at VCC VEE = 9.0 V
Logic level translation: to enable 5 V logic to communicate with 5 V analog signals
Typical ‘break before make’ built-in
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Multiple package options
Specified from 40 C to +85 C and 40 C to +125 C
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NXP Semiconductors
74HC4053; 74HCT4053
Triple 2-channel analog multiplexer/demultiplexer
6.2 Pin description
Table 2. Pin description
Symbol
E
VEE
GND
S1, S2, S3
1Y0, 2Y0, 3Y0
1Y1, 2Y1, 3Y1
1Z, 2Z, 3Z
VCC
Pin
6
7
8
11, 10, 9
12, 2, 5
13, 1, 3
14, 15, 4
16
7. Functional description
Description
enable input (active LOW)
supply voltage
ground supply voltage
select input
independent input or output
independent input or output
common output or input
supply voltage
Table 3.
Inputs
E
L
L
H
Function table [1]
Sn
L
H
X
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
8. Limiting values
Channel on
nY0 to nZ
nY1 to nZ
switches off
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to VSS = 0 V (ground).
Symbol
Parameter
Conditions
Min Max Unit
VCC supply voltage
[1] 0.5
+11.0
V
IIK input clamping current VI < 0.5 V or VI > VCC + 0.5 V - 20 mA
ISK
switch clamping current VSW < 0.5 V or VSW > VCC + 0.5 V
-
ISW switch current
0.5 V < VSW < VCC + 0.5 V
-
IEE supply current
-
20 mA
25 mA
20 mA
ICC
IGND
Tstg
Ptot
supply current
ground current
storage temperature
total power dissipation
DIP16 package
SO16, (T)SSOP16, and
DHVQFN16 package
-
-
65
[2] -
[3] -
50
50
+150
750
500
mA
mA
C
mW
mW
P
power dissipation
per switch
- 100 mW
[1] To avoid drawing VCC current out of terminal nZ, when switch current flows into terminals nYn, the voltage drop across the bidirectional
switch must not exceed 0.4 V. If the switch current flows into terminal nZ, no VCC current will flow out of terminals nYn, and in this case
there is no limit for the voltage drop across the switch, but the voltages at nYn and nZ may not exceed VCC or VEE.
[2] For DIP16 packages: above 70 C the value of Ptot derates linearly with 12 mW/K.
74HC_HCT4053
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 8 — 19 July 2012
© NXP B.V. 2012. All rights reserved.
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