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PDF UCB1510 Data sheet ( Hoja de datos )
| Número de pieza | UCB1510 | |
| Descripción | AC97 digital modem codec | |
| Fabricantes | NXP Semiconductors | |
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UCB1510
AC97 digital modem codec
Rev. 01 — 4 February 2000
Preliminary specification
1. Description
The UCB1510 is a single chip, integrated mixed signal telecom codec that can
directly be connected to a DAA and supports high speed modem protocols. The
general purpose I/O pins provide programmable inputs and/or outputs to the system.
The UCB1510 has a serial AClink interface intended to communicate to the system
controller. Both the codec input data and codec output data and the control register
data are multiplexed on this interface.
2. Features
s Sigma delta telecom codec with programmable sample rate, including digitally
controlled input voltage level, mute, loop back and clip detection functions. The
telecom codec can be directly connected to a Data Access Arrangement (DAA)
and includes a built in sidetone suppression circuit
s AClink (rev 2.1) interface with secondary codec support
s 3.3 V supply voltage and built in power saving modes make the UCB1510 optimal
for portable and battery powered applications
s 5 V tolerant interface for motherboard/PC add on
c
c s Maximum operating current 25 mA
s 8 general purpose IO pins for line interface control
s Interrupt detection driven wake up sequence for ring detect
s Low cost 12.288 MHz crystal
3. Applications
s Standalone modems
s Integrated modems
s Audio/Modem Riser (AMR) Cards
s Mobile Daughter Cards (MDC)
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1 page  
Philips Semiconductors
UCB1510
AC97 digital modem codec
7. Functional description
The functional description of the devices id described in Section 8 through
Section 15.
8. Telecom codec
The telecom codec contains an input channel, built up from a 64 times oversampling
sigma delta analog to digital converter (ADC) with digital decimation filters,
programmable gain and attenuation and built-in sidetone suppression circuit.
The output path consists of a digital up sample filter, a 64 time oversampling 4 bit
digital to analog converter (DAC) circuit with integrated filter followed by a differential
output driver, capable of directly driving a 600 Ω isolation transformer. The output
path includes a mute function. The telecom codec also incorporates loop back
modes, in which codec output path and the input path are connected in series. The
loop back tap and entry points are identified as circled letters in Figure 3, loop back
modes are described in the AClink register definition.
sidetone_enable
ADC[3:2]
TINP
TINN
SIDETONE
SUPPRESSION
CIRCUIT
ADC
J
H DIGITAL
14
DECIMATION
FILTER
G
TOUTP
E
TOUTN
D CDAC
DIGITAL
NOISE
14
SHAPER
B
DAC Mute
Fig 3. Telecom codec block diagram
9397 750 06856
Preliminary specification
The telecom sample rate (fst) is derived from the AC master clock and is
programmable using the sample rate registers. Not all AC97 specified sample rates
are supported, refer to Table 3 “Sampling frequencies” for details.
PCM data is transferred in the slot 5 of the AClink.
Rev. 01 — 4 February 2000
© Philips Electronics N.V. 2000. All rights reserved.
5 of 32
5 Page 
Philips Semiconductors
UCB1510
AC97 digital modem codec
11.2.4 Line 1 DAC/ADC Level
Table 11: Line 1 DAC/ADC Level Register
Register address: 0x46; default: 0x8080
Bit D15 D14 D13 D12
Symbol DAC
mute
Bit D7 D6 D5 D4
Symbol ADC
mute
D11 D10
D9
D8
D3
ADC3
D2
ADC2
D1
ADC1
D0
ADC0
Table 12: Description of Line1 DAC/ADC Level bits
Bit Symbol Function/Value
D15 DAC mute DAC section is active, but no signal will be sent.
D7 ADC mute ADC section is active, but no signal will be sent.
D3-D2 ADC[3:2] ADC Gain (0 -> 0 dB, 1 -> 6 dB, 2 -> 12 dB, 3 -> 18 dB)
D1-D0 ADC[1:0] These bits are ignored.
11.2.5 GPIO Pin Configuration
Table 13: GPIO Pin Configuration Register
Register address: 0x4C; default: 0x00FF
Bit D15 D14 D13 D12
Symbol
Bit D7 D6 D5 D4
Symbol GC7
GC6
GC5
GC4
D11
D3
GC3
D10
D2
GC2
D9
D1
GC1
D8
D0
GC0
The GPIO Pin Configuration register specifies whether a GPIO pin is configured for
input (1) or for output (0).
11.2.6 GPIO Pin Polarity
Table 14: GPIO Pin Polarity Register
Register address: 0x4E; default: 0xFFFF
Bit D15 D14 D13
Symbol
Bit D7 D6 D5
Symbol GP7
GP6
GP5
D12
D4
GP4
D11
D3
GP3
D10
D2
GP2
D9
D1
GP1
D8
D0
GP0
The GPIO Pin Polarity register defines GPIO Input Polarity (0 = Low, 1 = High) when
a GPIO pin is configured as an input.
9397 750 06856
Preliminary specification
Rev. 01 — 4 February 2000
© Philips Electronics N.V. 2000. All rights reserved.
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