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64F3048F16 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 64F3048F16
기능 HD64F3048F16
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64F3048F16 데이터시트, 핀배열, 회로
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Hitachi Single-Chip Microcomputer
H8/3048 Series
H8/3048
HD64F3048, HD6473048, HD6433048
H8/3047
HD6433047
H8/3045
HD6433045
H8/3044
HD6433044
Hardware Manual
ADE-602-073B




64F3048F16 pdf, 반도체, 판매, 대치품
2.9 Basic Operational Timing............................................................................................... 51
2.9.1 Overview......................................................................................................... 51
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2.9.2 On-Chip Memory Access Timing................................................................... 51
2.9.3 On-Chip Supporting Module Access Timing ................................................. 53
2.9.4 Access to External Address Space.................................................................. 54
Section 3 MCU Operating Modes........................................................................... 55
3.1 Overview......................................................................................................................... 55
3.1.1 Operating Mode Selection .............................................................................. 55
3.1.2 Register Configuration.................................................................................... 56
3.2 Mode Control Register (MDCR) .................................................................................... 57
3.3 System Control Register (SYSCR)................................................................................. 58
3.4 Operating Mode Descriptions......................................................................................... 60
3.4.1 Mode 1 ............................................................................................................ 60
3.4.2 Mode 2 ............................................................................................................ 60
3.4.3 Mode 3 ............................................................................................................ 60
3.4.4 Mode 4 ............................................................................................................ 60
3.4.5 Mode 5 ............................................................................................................ 60
3.4.6 Mode 6 ........................................................................................................... 60
3.4.7 Mode 7 ........................................................................................................... 61
3.5 Pin Functions in Each Operating Mode.......................................................................... 61
3.6 Memory Map in Each Operating Mode.......................................................................... 61
Section 4 Exception Handling.................................................................................. 71
4.1 Overview......................................................................................................................... 71
4.1.1 Exception Handling Types and Priority.......................................................... 71
4.1.2 Exception Handling Operation ....................................................................... 71
4.1.3 Exception Vector Table................................................................................... 72
4.2 Reset ............................................................................................................................... 73
4.2.1 Overview......................................................................................................... 73
4.2.2 Reset Sequence ............................................................................................... 73
4.2.3 Interrupts after Reset....................................................................................... 76
4.3 Interrupts......................................................................................................................... 77
4.4 Trap Instruction............................................................................................................... 78
4.5 Stack Status after Exception Handling ........................................................................... 79
4.6 Notes on Stack Usage ..................................................................................................... 80
Section 5 Interrupt Controller................................................................................... 81
5.1 Overview......................................................................................................................... 81
5.1.1 Features........................................................................................................... 81
5.1.2 Block Diagram................................................................................................ 82

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64F3048F16 전자부품, 판매, 대치품
8.3.2 I/O Address Registers (IOAR)........................................................................ 196
8.3.3 Execute Transfer Count Registers (ETCR)..................................................... 197
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8.3.4 Data Transfer Control Registers (DTCR) ....................................................... 199
8.4 Operation ........................................................................................................................ 205
8.4.1 Overview......................................................................................................... 205
8.4.2 I/O Mode......................................................................................................... 207
8.4.3 Idle Mode........................................................................................................ 209
8.4.4 Repeat Mode................................................................................................... 212
8.4.5 Normal Mode.................................................................................................. 215
8.4.6 Block Transfer Mode ...................................................................................... 218
8.4.7 DMAC Activation........................................................................................... 223
8.4.8 DMAC Bus Cycle ........................................................................................... 225
8.4.9 Multiple-Channel Operation........................................................................... 231
8.4.10 External Bus Requests, Refresh Controller, and DMAC................................ 232
8.4.11 NMI Interrupts and DMAC ............................................................................ 233
8.4.12 Aborting a DMA Transfer .............................................................................. 234
8.4.13 Exiting Full Address Mode............................................................................. 235
8.4.14 DMAC States in Reset State, Standby Modes, and Sleep Mode .................... 236
8.5 Interrupts......................................................................................................................... 237
8.6 Usage Notes .................................................................................................................... 238
8.6.1 Note on Word Data Transfer........................................................................... 238
8.6.2 DMAC Self-Access ........................................................................................ 238
8.6.3 Longword Access to Memory Address Registers........................................... 238
8.6.4 Note on Full Address Mode Setup.................................................................. 238
8.6.5 Note on Activating DMAC by Internal Interrupts .......................................... 239
8.6.6 NMI Interrupts and Block Transfer Mode ...................................................... 240
8.6.7 Memory and I/O Address Register Values ..................................................... 240
8.6.8 Bus Cycle when Transfer is Aborted .............................................................. 241
Section 9 I/O Ports....................................................................................................... 243
9.1 Overview......................................................................................................................... 243
9.2 Port 1............................................................................................................................... 246
9.2.1 Overview......................................................................................................... 246
9.2.2 Register Descriptions...................................................................................... 247
9.3 Port 2............................................................................................................................... 249
9.3.1 Overview......................................................................................................... 249
9.3.2 Register Descriptions...................................................................................... 250
9.4 Port 3............................................................................................................................... 253
9.4.1 Overview......................................................................................................... 253
9.4.2 Register Descriptions...................................................................................... 253
9.5 Port 4............................................................................................................................... 255

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64F3048F16

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