|
|
PDF PIO Data sheet ( Hoja de datos )
| Número de pieza | PIO | |
| Descripción | 32-bit Embedded Core Peripheral | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de PIO (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
|
No Preview Available !
( DataSheet : www.DataSheet4U.com )
Features
• Compatible with an Embedded 32-bit ARM7TDMI™ Processor
• Up to 32 Programmable I/O Lines
• Interrupt Generation on Event
• Glitch Filter
• Fully Scan Testable (up to 98% Fault Coverage)
• Can be Directly Connected to the Atmel Implementation
of the AMBA™ Peripheral Bus (APB) of the ARM7TDMI Microcontroller
• Multi-driver (Open Drain) Option
• Certain Options “Parametrizable” on Request:
• Number of Programmable Lines
• Glitch Filter Option
• Multi-driver (Open Drain) Option
• Reset State of PIO Status and Glitch Filter Status
Description
The Parallel Input/Output 1 (PIO1) 32-bit embedded core peripheral features 32 fully-
programmable input/output lines, each of which may be dedicated as general purpose
I/O or be multiplexed with a signal generated by another embedded peripheral, in
order to optimize the use of available package pins in the overall system-on-chip
design. The PIO1 controller provides a bit-maskable event driven internal interrupt
signal.
The PIO1 and other analog and digital modular embedded peripherals, together with a
choice of microprocessor and DSP cores, on-chip RAM, ROM, EEPROM and Flash
memory, as well as special purpose analog or digital user-developed blocks, allow
rapid and cost-effective design and implementation of an optimized system-on-chip.
The large range of functional blocks offers a realistic and efficient design pathway to
system-level integration (SLI).
The PIO1 is bus-compatible with the ARM7TDMI 32-bit microcontroller core. It can
also be used with other 32-bit MCU or DSP cores.
The PIO1 is supplied with comprehensive test vector sets. Atmel’s proprietary foundry
interface tools ensure a smooth transition from design to fabrication.
32-bit
Embedded Core
Peripheral
Parallel
Input/Output 1
(PIO1)
www.DataSheet4U.com
Rev. 1321C–03/01
1
1 page  
PIO1
Functional
Description
The 32-bit PIO1 peripheral is fully compatible with an embedded ARM7TDMI processor.
The PIO peripheral features 32 fully-programmable I/O lines, each of which may be mul-
tiplexed with an on-chip peripheral signal.
The device can also provide a bit-maskable event driven on-chip interrupt signal.
The PIO1 peripheral is fully-controllable via five sets of three 32-bit registers; pin data
and interrupt source conditions are available to user software via two 32-bit regis-
ters.Figure 3 illustrates PIO1 functionality and the effect of register programming as
described in the following sections
Figure 3. .PIO1 Control and Status Register Architecture
PIO_OSR
Pad Output Enable
0
1
0
1 PIO_PSR
Pad Output
PIO_MDSR
0
1
Pad
PIO_ODSR
1
0
Pad Input
PIO_MDSR
0
Filter
1
1
0 PIO_PSR
PIO_IFSR
PIO_PDSR
Event
Detection
PIO_ISR
PIO_IMR
Peripheral
Output
Enable
Peripheral
Output
Peripheral
Input
PIOIRQ
1321C–03/01
5
5 Page 
PIO1
PIO Output Enable
For the bit configuration of the register, see “l User Interface Register Descriptions” on
page 10
PIO Output Enable Register
Register Name:
PIO_OER
Access Type:
Write-only
This register is used to enable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_OER has
no effect on the pin, but the information is stored. The register is programmed as follows:
1 = Enables the PIO output on the corresponding pin.
0 = No effect.
PIO Output Disable Register
Register Name:
PIO_ODR
Access Type:
Write-only
This register is used to disable PIO output drivers. If the pin is driven by an internally connected peripheral, PIO_ODR has
no effect on the pin, but the information is stored. The register is programmed as follows:
1 = Disables the PIO output on the corresponding pin.
0 = No effect.
PIO Output Status Register
Register Name:
PIO_OSR
Access Type:
Read-only
Reset Value:
0
This register shows the PIO pin control (output enable) status which is programmed via PIO_OER and PIO_ODR. The
defined value is effective only if the pin is controlled by the PIO. The register reads as follows:
1 = The corresponding PIO is output on this line.
0 = The corresponding PIO is input on this line.
Glitch Filtering
For the bit configuration of the register, see “l User Interface Register Descriptions” on page 10.
PIO Input Filter Enable Register
Register Name:
PIO_IFER
Access Type:
Write-only
This register is used to enable input glitch filters; it affects the data read from the pin whether or not the PIO is enabled. The
register is programmed as follows:
1 = Enables the glitch filter on the corresponding pin.
0 = No effect.
PIO Input Filter Disable Register
Register Name:
IO_IFDR
Access Type:
Write-only
This register is used to disable input glitch filters. It affects the data read from the pin whether or not the PIO is enabled. The
register is programmed as follows:
1 = Disables the glitch filter on the corresponding pin.
0 = No effect.
1321C–03/01
11
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet PIO.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| PI-15xxxx | PULSE TRANSFORMERS |  Premo |
| PI-18xxxx | PULSE TRANSFORMERS | Premo |
| PI-23xxxx | PULSE TRANSFORMERS | Premo |
| PI-800 | SURFACE MOUNT-CERAMIC PIN DIODE |  MCE |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |