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PDF PCF5212 Data sheet ( Hoja de datos )
| Número de pieza | PCF5212 | |
| Descripción | MCF5212 | |
| Fabricantes | Motorola Semiconductors | |
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( DataSheet : www.DataSheet4U.com )
MCF5213 ColdFire® Integrated
Microcontroller Reference Manual
Additional Devices Supported:
MCF5211
MCF5212
MCF5213RM
Rev 1.1
07/2005
www.DataSheet4U.com
1 page  
Contents
Paragraph
Number
Title
Page
Number
3.4
3.5
3.6
3.7
3.7.1
3.7.2
3.7.3
3.7.4
3.7.5
3.7.6
3.7.7
3.7.8
3.7.9
3.7.10
3.7.11
3.7.12
3.7.13
3.7.14
3.7.15
3.8
3.8.1
3.8.2
3.9
3.10
3.11
3.12
3.13
Additions to the Instruction Set Architecture ............................................................... 3-11
Exception Processing Overview ................................................................................... 3-12
Exception Stack Frame Definition ................................................................................ 3-14
Processor Exceptions .................................................................................................... 3-15
Access Error Exception ............................................................................................ 3-15
Address Error Exception ........................................................................................... 3-16
Illegal Instruction Exception ..................................................................................... 3-16
Divide-By-Zero ......................................................................................................... 3-16
Privilege Violation .................................................................................................... 3-16
Trace Exception ........................................................................................................ 3-16
Unimplemented Line-A Opcode ............................................................................... 3-17
Unimplemented Line-F Opcode ............................................................................... 3-17
Debug Interrupt ......................................................................................................... 3-17
RTE and Format Error Exception ............................................................................. 3-17
TRAP Instruction Exception ..................................................................................... 3-17
Interrupt Exception ................................................................................................... 3-18
Fault-on-Fault Halt ................................................................................................... 3-18
Reset Exception ........................................................................................................ 3-18
Reset Vector .............................................................................................................. 3-21
Instruction Execution Timing ....................................................................................... 3-24
Timing Assumptions ................................................................................................. 3-24
MOVE Instruction Execution Times ........................................................................ 3-25
Standard One Operand Instruction Execution Times ................................................... 3-26
Standard Two Operand Instruction Execution Times ................................................... 3-27
Miscellaneous Instruction Execution Times ................................................................. 3-28
MAC Instruction Execution Times Check CF2 MAC (EMAC #’s) ............................ 3-29
Check CF3/CF2 MAC/EMACBranch Instruction Execution Times ........................... 3-30
4.1
4.1.1
4.1.2
4.1.3
4.1.4
4.2
Chapter 4
Hardware Multiply/Accumulate (MAC) Unit
Overview ......................................................................................................................... 4-1
MAC Programming Model ......................................................................................... 4-2
General Operation ....................................................................................................... 4-3
MAC Instruction Set Summary .................................................................................. 4-4
Data Representation .................................................................................................... 4-5
MAC Instruction Execution Timings ............................................................................. 4-5
Freescale Semiconductor
MCF5213 Reference Manual, Rev. 1.1
Preliminary
iii
5 Page 
Contents
Paragraph
Number
Title
Page
Number
12.3
12.3.1
12.3.2
12.3.3
12.3.4
12.3.5
12.3.6
12.3.6.1
12.3.7
12.4
Register Descriptions .................................................................................................... 12-5
Interrupt Pending Registers (IPRHn, IPRLn) ........................................................... 12-5
Interrupt Mask Register (IMRHn, IMRLn) .............................................................. 12-6
Interrupt Force Registers (INTFRCHn, INTFRCLn) ............................................... 12-8
Interrupt Request Level Register (IRLRn) ............................................................. 12-10
Interrupt Acknowledge Level and Priority Register (IACKLPRn) ........................ 12-10
Interrupt Control Register (ICRnx, (x = 1, 2,..., 63)) .............................................. 12-11
Interrupt Sources ................................................................................................. 12-11
Software and Level n IACK Registers (SWIACKR, L1IACK–L7IACK) ............. 12-14
Low-Power Wakeup Operation .................................................................................. 12-15
13.1
13.2
13.3
13.4
13.4.1
13.4.2
13.4.2.1
13.4.2.2
13.4.2.3
13.4.2.4
13.4.2.5
13.4.2.6
Chapter 13
Edge Port Module (EPORT)
Introduction ................................................................................................................... 13-1
Low-Power Mode Operation ........................................................................................ 13-1
Interrupt/General-Purpose I/O Pin Descriptions ........................................................... 13-2
Memory Map and Registers .......................................................................................... 13-3
Memory Map ............................................................................................................ 13-3
Registers .................................................................................................................... 13-3
EPORT Pin Assignment Register (EPPAR) ......................................................... 13-3
EPORT Data Direction Register (EPDDR) .......................................................... 13-4
Edge Port Interrupt Enable Register (EPIER) ...................................................... 13-5
Edge Port Data Register (EPDR) .......................................................................... 13-5
Edge Port Pin Data Register (EPPDR) ................................................................. 13-6
Edge Port Flag Register (EPFR) ........................................................................... 13-6
14.1
14.1.1
14.2
14.3
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.4
Chapter 14
DMA Controller Module
Overview ....................................................................................................................... 14-1
DMA Module Features ............................................................................................. 14-2
DMA Transfer Overview .............................................................................................. 14-3
DMA Controller Module Programming Model ............................................................ 14-3
Source Address Registers (SAR0–SAR3) ................................................................ 14-4
Destination Address Registers (DAR0–DAR3) ....................................................... 14-5
Byte Count Registers (BCR0–BCR3) ...................................................................... 14-5
DMA Control Registers (DCR0–DCR3) .................................................................. 14-5
DMA Status Registers (DSR0–DSR3) ..................................................................... 14-8
DMA Controller Module Functional Description ........................................................ 14-8
Freescale Semiconductor
MCF5213 Reference Manual, Rev. 1.1
Preliminary
ix
11 Page | ||
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| PDF Descargar | [ Datasheet PCF5212.PDF ] | |
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