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JS28F256P30B85 데이터시트, 핀배열, 회로
( DataSheet : www.DataSheet4U.com )
Intel StrataFlash® Embedded Memory
(P30)
1-Gbit P30 Family
Datasheet
Product Features
High performance
Security
— 85/88 ns initial access
— One-Time Programmable Registers:
— 40 MHz with zero wait states, 20 ns clock-to-
data output synchronous-burst read mode
• 64 unique factory device identifier bits
• 64 user-programmable OTP bits
— 25 ns asynchronous-page read mode
• Additional 2048 user-programmable OTP bits
— 4-, 8-, 16-, and continuous-word burst mode
— Selectable OTP Space in Main Array:
— Buffered Enhanced Factory Programming
(BEFP) at 5 µs/byte (Typ)
• 4x32KB parameter blocks + 3x128KB main
blocks (top or bottom configuration)
— 1.8 V buffered programming at 7 µs/byte (Typ)
— Absolute write protection: VPP = VSS
Architecture
— Multi-Level Cell Technology: Highest Density
at Lowest Cost
— Power-transition erase/program lockout
— Individual zero-latency block locking
— Individual block lock-down
— Asymmetrically-blocked architecture
Software
— Four 32-KByte parameter blocks: top or
— 20 µs (Typ) program suspend
bottom configuration
— 20 µs (Typ) erase suspend
— 128-KByte main blocks
— Intel® Flash Data Integrator optimized
Voltage and Power
— VCC (core) voltage: 1.7 V – 2.0 V
— VCCQ (I/O) voltage: 1.7 V – 3.6 V
— Standby current: 55 µA (Typ) for 256-Mbit
— Basic Command Set and Extended Command
Set compatible
— Common Flash Interface capable
Density and Packaging
— 4-Word synchronous read current:
13 mA (Typ) at 40 MHz
— 64/128/256-Mbit densities in 56-Lead TSOP
package
Quality and Reliability
— Operating temperature: –40 °C to +85 °C
— 64/128/256/512-Mbit densities in 64-Ball
Intel® Easy BGA package
• 1-Gbit in SCSP is –30 °C to +85 °C
— 64/128/256/512-Mbit and 1-Gbit densities in
— Minimum 100,000 erase cycles per block
Intel® QUAD+ SCSP
— ETOX™ VIII process technology (130 nm)
— 16-bit wide data bus
The Intel StrataFlash® Embedded Memory (P30) product is the latest generation of Intel
StrataFlash® memory devices. Offered in 64-Mbit up through 1-Gbit densities, the P30 device
brings reliable, two-bit-per-cell storage technology to the embedded flash market segment.
Benefits include more density in less space, high-speed interface, lowest cost-per-bit NOR
device, and support for code and data storage. Features include high-performance synchronous-
burst read mode, fast asynchronous access times, low power, flexible security options, and three
industry standard package choices.
The P30 product family is manufactured using Intel® 130 nm ETOX™ VIII process technology.
www.DataSheet4U.com
Order Number: 306666, Revision: 001
April 2005




JS28F256P30B85 pdf, 반도체, 판매, 대치품
1-Gbit P30 Family
10.0 Read Operations .................................................................................................................... 53
10.1 Asynchronous Page-Mode Read........................................................................................ 53
10.2 Synchronous Burst-Mode Read.......................................................................................... 53
10.3 Read Configuration Register .............................................................................................. 54
10.3.1 Read Mode ............................................................................................................ 55
10.3.2 Latency Count........................................................................................................ 55
10.3.3 WAIT Polarity......................................................................................................... 57
10.3.4 Data Hold............................................................................................................... 58
10.3.5 WAIT Delay............................................................................................................ 59
10.3.6 Burst Sequence ..................................................................................................... 59
10.3.7 Clock Edge ............................................................................................................ 59
10.3.8 Burst Wrap............................................................................................................. 59
10.3.9 Burst Length .......................................................................................................... 60
11.0 Programming Operations .................................................................................................. 61
11.1 Word Programming............................................................................................................. 61
11.1.1 Factory Word Programming................................................................................... 62
11.2 Buffered Programming........................................................................................................ 62
11.3 Buffered Enhanced Factory Programming ......................................................................... 63
11.3.1 BEFP Requirements and Considerations .............................................................. 64
11.3.2 BEFP Setup Phase................................................................................................ 64
11.3.3 BEFP Program/Verify Phase ................................................................................. 64
11.3.4 BEFP Exit Phase ................................................................................................... 65
11.4 Program Suspend............................................................................................................... 65
11.5 Program Resume................................................................................................................ 66
11.6 Program Protection............................................................................................................. 66
12.0 Erase Operations................................................................................................................... 67
12.1
12.2
12.3
12.4
Block Erase......................................................................................................................... 67
Erase Suspend ................................................................................................................... 67
Erase Resume .................................................................................................................... 68
Erase Protection ................................................................................................................. 68
13.0 Security Modes....................................................................................................................... 69
13.1 Block Locking...................................................................................................................... 69
13.1.1 Lock Block ............................................................................................................. 69
13.1.2 Unlock Block .......................................................................................................... 69
13.1.3 Lock-Down Block ................................................................................................... 69
13.1.4 Block Lock Status .................................................................................................. 70
13.1.5 Block Locking During Suspend.............................................................................. 70
13.2 Selectable One-Time Programmable Blocks...................................................................... 71
13.3 Protection Registers ........................................................................................................... 72
13.3.1 Reading the Protection Registers .......................................................................... 73
13.3.2 Programming the Protection Registers.................................................................. 73
13.3.3 Locking the Protection Registers ........................................................................... 74
14.0 Special Read States ............................................................................................................. 75
14.1 Read Status Register.......................................................................................................... 75
14.1.1 Clear Status Register............................................................................................. 76
14.2 Read Device Identifier ........................................................................................................ 76
April 2005
4
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet

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JS28F256P30B85 전자부품, 판매, 대치품
1.0
1.1
1-Gbit P30 Family
Introduction
This document provides information about the Intel StrataFlash® Embedded Memory (P30) device
and describes its features, operation, and specifications.
Nomenclature
1.8 V :
3.0 V :
9.0 V :
VCC (core) voltage range of 1.7 V – 2.0 V
VCCQ (I/O) voltage range of 1.7 V – 3.6 V
VPP voltage range of 8.5 V – 9.5 V
Block :
A group of bits, bytes,1-Gbit P30 Family or words within the
flash memory array that erase simultaneously when the Erase
command is issued to the device. The 1-Gbit P30 Family has
two block sizes: 32-KByte and 128-KByte.
Main block :
An array block that is usually used to store code and/or data.
Main blocks are larger than parameter blocks.
Parameter block :
An array block that is usually used to store frequently changing
data or small system parameters that traditionally would be
stored in EEPROM.
Top parameter device :
A device with its parameter blocks located at the highest
physical address of its memory map.
Bottom parameter device : A device with its parameter blocks located at the lowest
physical address of its memory map.
1.2 Acronyms
BEFP :
CUI :
MLC :
OTP :
PLR :
PR :
RCR :
Buffer Enhanced Factory Programming
Command User Interface
Multi-Level Cell
One-Time Programmable
Protection Lock Register
Protection Register
Read Configuration Register
Datasheet
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
April 2005
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Intel StrataFlash Embedded Memory

Intel Corporation
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