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P-80C52 데이터시트 PDF




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부품번호 P-80C52 기능
기능 (P-80C32 / P-80C52) CMOS 8-Bit Microcontroller
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P-80C52 데이터시트, 핀배열, 회로
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80C32/80C52
CMOS 0 to 44 MHz Single Chip 8–bit Microcontroller
1. Description
TEMIC’s 80C52 and 80C32 are high performance
CMOS versions of the 8052/8032 NMOS single chip 8
bit Microcontroller.
The fully static design of the TEMIC 80C52/80C32
allows to reduce system power consumption by bringing
the clock frequency down to any value, even DC,
without loss of data.
The 80C52 retains all the features of the 8052: 8 K bytes
of ROM; 256 bytes of RAM; 32 I/O lines; three 16 bit
timers; a 6-source, 2-level interrupt structure; a full
duplex serial port; and on-chip oscillator and clock
circuits. In addition, the 80C52 has 2
D 80C32: Romless version of the 80C52
D 80C32/80C52-L16: Low power version
VCC: 2.7 – 5.5 V Freq: 0-16 MHz
D 80C32/80C52-12: 0 to 12 MHz
D 80C32/80C52-16: 0 to 16 MHz
D 80C32/80C52-20: 0 to 20 MHz
D 80C32/80C52-25: 0 to 25 MHz
D 80C32/80C52-30: 0 to 30 MHz
D 80C32/80C52-36: 0 to 36 MHz
software-selectable modes of reduced activity for
further reduction in power consumption. In the idle
mode the CPU is frozen while the RAM, the timers, the
serial port and the interrupt system continue to function.
In the power down mode the RAM is saved and all other
functions are inoperative.
The 80C32 is identical to the 80C52 except that it has no
on-chip ROM. TEMIC’s 80C52/80C32 are
manufactured using SCMOS process which allows them
to run from 0 up to 44 MHz with VCC = 5 V.
TEMIC’s 80C52 and 80C32 are also available at
16 MHz with 2.7 V < VCC < 5.5 V.
D 80C32-40: 0 to 40 MHz(1)
D 80C32-42: 0 to 42 MHz(1)
D 80C32-44: 0 to 44 MHz(1)
Notes:
1. 0 to 70_C temperature range.
2. For other speed and temperature range availability, please
contact your sales office.
2. Features
D Power control modes
D 256 bytes of RAM
D 8 Kbytes of ROM (80C52)
D 32 programmable I/O lines
D Three 16 bit timer/counters
D 64 K program memory space
D 64 K data memory space
D Fully static design
D 0.8µ CMOS process
D Boolean processor
D 6 interrupt sources
D Programmable serial port
D Temperature range: commercial, industrial, automotive,
military
3. Optional
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D Secret ROM: Encryption
D Secret TAG: Identification number
Rev. I September 18, 1998
1




P-80C52 pdf, 반도체, 판매, 대치품
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80C32/80C52
5. Pin Description
5.1. VSS
Circuit ground potential.
5.2. VCC
Supply voltage during normal, Idle, and Power Down operation.
5.3. Port 0
Port 0 is an 8 bit open drain bi-directional I/O port. Port 0 pins that have 1’s written to them float, and in that state can
be used as high-impedance inputs.
Port 0 is also the multiplexed low-order address and data bus during accesses to external Program and Data Memory.
In this application it uses strong internal pullups when emitting 1’s. Port 0 also outputs the code bytes during program
verification in the 80C52. External pullups are required during program verification. Port 0 can sink eight LS TTL
inputs.
5.4. Port 1
Port 1 is an 8 bit bi-directional I/O port with internal pullups. Port 1 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 1 pins that are externally being pulled
low will source current (IIL, on the data sheet) because of the internal pullups.
Port 1 also receives the low-order address byte during program verification. In the 80C52, Port 1 can sink/ source three
LS TTL inputs. It can drive CMOS inputs without external pullups.
2 inputs of PORT 1 are also used for timer/counter 2 :
P1.0 [T2]: External clock input for timer/counter 2. P1.1 [T2EX]: A trigger input for timer/counter 2, to be reloaded
or captured causing the timer/counter 2 interrupt.
5.5. Port 2
Port 2 is an 8 bit bi-directional I/O port with internal pullups. Port 2 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 2 pins that are externally being pulled
low will source current (ILL, on the data sheet) because of the internal pullups. Port 2 emits the high-order address
byte during fetches from external Program Memory and during accesses to external Data Memory that use 16 bit
addresses (MOVX @DPTR). In this application, it uses strong internal pullups when emitting 1’s. During accesses to
external Data Memory that use 8 bit addresses (MOVX @Ri), Port 2 emits the contents of the P2 Special Function
Register.
It also receives the high-order address bits and control signals during program verification in the 80C52. Port 2 can
sink/source three LS TTL inputs. It can drive CMOS inputs without external pullups.
5.6. Port 3
Port 3 is an 8 bit bi-directional I/O port with internal pullups. Port 3 pins that have 1’s written to them are pulled high
by the internal pullups, and in that state can be used as inputs. As inputs, Port 3 pins that are externally being pulled
low will source current (ILL, on the data sheet) because of the pullups. It also serves the functions of various special
features of the TEMIC 51 Family, as listed below.
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4 Rev. I September 18, 1998

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P-80C52 전자부품, 판매, 대치품
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80C32/80C52
6.1. Idle Mode
The instruction that sets PCON.0 is the last instruction executed before the Idle mode is activated. Once in the Idle
mode the CPU status is preserved in its entirety: the Stack Pointer, Program Counter, Program Status Word,
Accumulator, RAM and all other registers maintain their data during idle. Table 1. describes the status of the external
pins during Idle mode.
There are three ways to terminate the Idle mode. Activation of any enabled interrupt will cause PCON.0 to be cleared
by hardware, terminating Idle mode. The interrupt is serviced, and following RETI, the next instruction to be executed
will be the one following the instruction that wrote 1 to PCON.0.
The flag bits GF0 and GF1 may be used to determine whether the interrupt was received during normal execution or
during the Idle mode. For example, the instruction that writes to PCON.0 can also set or clear one or both flag bits.
When Idle mode is terminated by an enabled interrupt, the service routine can examine the status of the flag bits.
The second way of terminating the Idle mode is with a hardware reset. Since the oscillator is still running, the hardware
reset needs to be active for only 2 machine cycles (24 oscillator periods) to complete the reset operation.
6.2. Power Down Mode
The instruction that sets PCON.1 is the last executed prior to entering power down. Once in power down, the oscillator
is stopped. The contents of the onchip RAM and the Special Function Register is saved during power down mode. The
hardware reset initiates the Special Fucntion Register. In the Power Down mode, VCC may be lowered to minimize
circuit power consumption. Care must be taken to ensure the voltage is not reduced until the power down mode is
entered, and that the voltage is restored before the hardware reset is applied which freezes the oscillator. Reset should
not be released until the oscillator has restarted and stabilized.
Table 1. describes the status of the external pins while in the power down mode. It should be noted that if the power
down mode is activated while in external program memory, the port data that is held in the Special Function Register
P2 is restored to Port 2. If the data is a 1, the port pin is held high during the power down mode by the strong pullup,
T1, shown in Figure 4.
Mode
Idle
Idle
Power Down
Power Down
Table 1. Status of the external pins during idle and power down modes
Program Memory
Ale PSEN PORT0
PORT1
PORT2
Internal
1
1
Port Data
Port Data
Port Data
External
1
1
Floating
Port Data
Address
Internal
0
0
Port Data
Port Data
Port Data
External
0
0
Floating
Port Data
Port Data
PORT3
Port Data
Port Data
Port Data
Port Data
6.3. Stop Clock Mode
Due to static design, the TEMIC 80C32/C52 clock speed can be reduced until 0 MHz without any data loss in memory
or registers. This mode allows step by step utilization, and permits to reduce system power consumption by bringing
the clock frequency down to any value. At 0 MHz, the power consumption is the same as in the Power Down Mode.
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Rev. I September 18, 1998
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부품번호상세설명 및 기능제조사
P-80C52

(P-80C32 / P-80C52) CMOS 8-Bit Microcontroller

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