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부품번호 | UM6845A 기능 |
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기능 | CRT Controller | ||
제조업체 | UMC | ||
로고 | |||
(l)UMC
UM6845/UM6845A/UM6845B
CRT Controller
Features
• Applications include smart, programmable, intelligent
CRT terminals; video games; information display
• Alphanumeric, semi-graphic, and full graphic capa-
bility
• Fully programmable via processor data bus and can
generate timing ·for almost any alphanumeric screen
density
• Single +5 volt supply, TTL compatibl-e I/O, NMOS
Technology
• Hardware scrolling by page, line or character
• Provides CPU's with synchronous signals to external
device
• Programmabfe cursor format
• Light pen registers and input strobe signal to latch the
light pen position on screen
• Line buffer-less operation. No external DMA required.
Reading screen memory is mutliplexed between CRTC
and CPU
• Programmable interlace or non- interlace scan
• 14-bit wide display memory reading address
General Description
The CRTC UM6845 family are LSI controllers designed
to provide an interface for microcomputers to raster
scan type CRT displays. The CRTC belongs to the
MC 6800 LSI Family and has full compatibility with
CPU in both data lines and control lines. Its primary
function is to generate timing signals which are necessary
for raster-scan type CRT displays according to the speci-
fication programmed by the .cPU.
Pin Configuration
VSS
RES
lPSTB
MAO
MAl
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MAg
MAlO
MAll
MA12
MA13
DISPTMG
CUDISP
VCC
VSYNC
HSYNC
RAO
RAl
RA2
RA3
RA4
DO
Dl
D2
D3
D4
D5
D6
D7
CS
RS
E
R/W
ClK
5-3
A. C. Characteristics
(Vcc=5V±5%, vss=Ov, TA=-20"-'+75°C)
BUS TIMING CHARACTERISTIC
MPU READ TIMING
UM6845/ UM6845A / UM6845B
Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Enable Rise and Fall Time
Address Set Up Time
Data Delay Time
Data Hold Time
Address Hold Time
Data Access Time
* See Fig-3
Symbol
tcyc E
PWEH
PWEL
tEr, tEf
tAS
tDDR
tH
tAH
tACC
UM6845
Min. Typ. Max.
UM6845A
Min. Typ. Max.
UM6845B
Units
Min. Typ. Max.
1.0 - - 0.666 - - 0.5 - - J.1,S
0.45 -
- 0.280 -
- 0.22 -
- J.1,S
0.40 -
- 0.280 -
- 0.21 -
- J.1,S
- - 25 - - 25 - - 25 J.1,S
140 -
- 140 - -
70 -
- nS
- - 320 - - 200 - - 180 nS
10 -
-
10 -
-
10 - - nS
10 - - 10 - - 10 - - nS
- - 460 - - 360 - - 250 nS
MPU WRITE TIMING
Item
Enable Cycle Time
Enable "High" Pulse Width
Enable "Low" Pulse Width
Enable Rise and Fall Time
Address Set Up Time
Data Set Up Time
Data Hold Time
Address Hold Time
* See Fig-4
Symbol
tcycE
PWEH
PWEL
tEr, tEf
tAS
tDSW
tH
tAH
UM6845
UM6845A
Min.
1.0
Typ.
-
M, ax.
"
-
Min.
0.666
Typ.
-
Max.
-
UM6845B
Units
Min. Typ. Max.
0.5 - - J.1,S
0.45 -
~ 0.280 -
- 0.22 -
- J.1,S
0.40 -
- 0.280 -
- 0.21 -
- J.1,S
- - 25 - - 25 - - 25 nS
140 - - 140 - - 70 - - nS
195 - - 80 - - 60 - - nS
10 - -
10 - -
10 - - nS
10 - -
10 - -
10 -
- nS
4페이지 UM6845/ UM6845A / UM68458
Typical Crt Controller Application Block Diagram
~----~--------~~------------~----------------------- AB
- - - - - - - - - - - - - - - - - - - - - - - - - . - - - - - - DB Primary Bus
CURSOR
DISPLAY
ENABLE
HS VS
ROW ADDRESSES
5
Figure 7. Typical CRT Controller Application
CRT Screen Format and Time Chart
REGISTERS PR.OGRAMMED VALUE
Register
RO
Rl
R2
R3
R4
R5
R6
R7
R8
R9
Rl0
Rll
R12
R13
R14
R15
R16
R17
Register Name
Horizontal Total
Horizontal Displayed
Horizontal Sync Position
Sync Width
Vertical Total
Vertical Total Adjust
Vertical Displayed
Vertical Sync Position
Interlace & Skew
Max. Raster Address
Cu rsor Start Raster
Cursor End Raster
Start Address (H)
Start Address (L)
Cursor (H)
Cursor (L)
Light Pen (H)
Light Pen L (L)
Specified Value
Nht+l
Nhd
Nhsp+ 1
Nvsw , Nhsw
Nvt+l
Nadj
Nvd
Nvsp + 1
Nr+l/Nr+2
NCSTART
NCEND
0
0
Programmed (Written) Value
Nht
Nhd
Nhsp
Nvsw , Nhsw
Nvt
Nadj
Nvd
Nvsp
I
Nr
5-9
7페이지 | |||
구 성 | 총 23 페이지수 | ||
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부품번호 | 상세설명 및 기능 | 제조사 |
UM6845 | CRT Controller | UMC |
UM6845A | CRT Controller | UMC |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |