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Número de pieza | UM6104 | |
Descripción | 1K x 4 CMOS SRAM | |
Fabricantes | UMC | |
Logotipo | ||
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============ UM6104
1K x 4 CMOS SRAM
Features
• Single + 5V power supply
• Low power standby
• Low power operation
• Fast Access time ........ , 120/150/200/250 ns max.
• Data retention . . . . . . . . . . . . . . . . . . .. 2.0V min.
• Three-state outputs
• On-chip address register
• Synchronous circuitry
• Standard 18 pin DIP package
• TTL compatible input/output
General Description
The UM6104 is a 1024x4 fu IIy stat ic CMOS. RAM. The
device utilizes synchronous circuitry to achieve perform-
ance and low power operation.
Pin Configuration
Block Diagram
On chip latches are provided for the addresses allowing
efficient interfacing with microprocessor systems. The data
output can be forced to a high impedance state for use in
expanded memory systems.
LATCHED
ADDRESS
REGISTER
ROW
DECODER
MEMORY
MATRIX
64x64
VCC
GND
1/01 0--+----1:::::1_------1
1/02 o--H.....--I..::::I~ . - - - - - - 1
1/03 0-+-+_1>----' I--Il;:::::'::":':';:~
I/04 o--t-I-+1~-----'
WE 0----1
LATCHED
ADDRESS
REGISTER
2-18
1 page ·.UMC
Read Modify Write Cycle Timing Diagram
UM61 04
A-l--tA-I.s-;~-A-L.l.tcI:--t-A-H~
---------~I~~-------------tCE
.~}
I\~" _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _,il~~-----tCE----~1 ~
two--a_tRS-~-
I/O
(OUT)
I/O
(IN)
HIGH-Z
Ordering. 1nformation
Part Number
UM6104
UM6104-2
UM6104-3
UM6104-4
UM6104J
UM6104J-2
UM6104J-3
UM6104J-4
Access Time
(Max.)
250 ns
200 ns
150 ns
120 ns
250ns
200 ns
150 ns
120 ns
Package
Plastic
Plastic
Plastic
Plastic
CERDIP
CERDIP
CERDIP
CERDIP
2-22
5 Page |
Páginas | Total 5 Páginas | |
PDF Descargar | [ Datasheet UM6104.PDF ] |
Número de pieza | Descripción | Fabricantes |
UM6104 | 1K x 4 CMOS SRAM | UMC |
UM6104-1 | 1K x 4 CMOS SRAM | UMC |
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