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UG01 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 UG01
기능 (UG01 - UG09) 0.6um ULC
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UG01 데이터시트, 핀배열, 회로
www.DataSheet4U.com
0.6µm ULC Series
UG Series
Description
The UG series of ULCs is well suited for conversion of
medium- to-large sized CPLDs and FPGAs. Devices are
implemented in high-performance CMOS technology
with 0.6-µm (drawn) channel lengths, and are capable of
supporting flip-flop toggle rates of 350 MHz, operating
clock frequencies up to 150 MHz and input to output
delays as fast as 5 ns.
The architecture of the UG series allows for efficient
conversion of many PLD architectures and FPGA
device types. A compact RAM cell, along with the large
number of available gates allows the implementation of
RAM in FPGA architectures that support this feature, as
well as JTAG boundary-scan and scan-path testing.
Conversion to the UG series of ULC can provide a
significant reduction in operating power when
compared to the original PLD or FPGA. This is
especially true when compared to many PLD and CPLD
architecture devices, which typically consume 100 mA
or more even when not being clocked. The UG series has
a very low standby consumption of 0.4 nA/gate
typically, which would yield a standby current of 4 mA
on a 10,000 gate design. Operating consumption is a
strict function of clock frequency, which typically
results in a power reduction of 50% to 90% depending
on the device being compared.
The UG series provides several options for output
buffers, including a variety of drive levels up to 24 mA.
Schmitt trigger inputs are also an option. A number of
techniques are used for improved noise immunity and
reduced EMC emissions, including: several
independent power supply busses and internal
decoupling for isolation; slew rate limited outputs are
also available as required.
The UG series is designed to allow conversions of high
performance 3.3V devices as well as 5.0V devices.
Support of mixed supply conversions is also possible,
allowing optimal trade-offs between speed and power
consumption.
Features
D High performance ULC family suitable for
medium- to large-sized CPLDs and FPGAs
D Conversions to over 200,000 FPGA gates
D Pin counts to over 300 pins
D Any pin-out matched due to limited number of
dedicated pads
D Advanced 0.6-µm (drawn)/0.45-µm (effective)
feature size
D Triple-layer or dual-layer metal CMOS
technology
D High speed performance:
– 250-ps typical cell delay
– 350-MHz toggle rate
D Full range of packages: DIP, SOIC, LCC/PLCC,
PQFP/TQFP, PGA/PPGA
D 3.3V and/or 5.0V operation.
D Low quiescent current: 0.4 nA/gate
D Available in commercial, industrial, automotive,
military and space grades.
www.DataSheet4U.com
Rev. B 25 May. 98
5–1




UG01 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
UG Series
Internal Timing Characteristics
These timing parameters for selected macro cells are
provided for information only. Only pin-to-pin timing
characteristics are guaranteed for ULCs, and the actual
specification is determined by the original FPGA or
PLD data sheet plus any specific parameters that are
agreed to separately by TEMIC.
Conditions: VDD = 5 V, Typical Process, Statistical Wire Length. All delays measured at VIN/VOUT = 2.5 V.
Macro Type
Parameter
Symbol
Min
Maxa
Maxb
Units
2-Input NAND
NAND2
0.39 0.56
4-Input NAND
Inverter
Inverting Tri-State Buffer
NAND4
INV
TRISTAN
Resetable Latch
LATCHR
D Flip-Flop with Reset
FDFFR
TTL Compatible Input
Buffer
BUFINTTL
TTL Compatible I/O Buffer
Input Mode
BIOT12
Output Buffer
BOUT6
Propagation Time
Enable Time
Setup Time
Hold Time
Pulse Width
Propagation Time
Enable Time
Reset Time
Setup Time
Hold Time
Pulse Width
Clock Delay Time
Reset Time
Propagation Time
TTL Compatible I/O Buffer
BIOT12
Tri-State Output Buffer
B3STA12
Enable Time
Propagation Time
Enable Time
tPD
tEN
tSU
tH
tPW
tDQ
tEN
tRN
tSU
tH
tPW
tCQ
tRN
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPLH
tPZH
tPZL
tPLH
tPHL
tPZH
tPZL
0.68 0.88
0.41 0.68
0.74 0.99
0.69 0.97
0.60
0.00
0.97 1.25
1.22 1.49
0.87 1.10
0.40
0.00
0.60
0.95 1.22
0.81 0.94
0.80 0.95
0.68 0.74
0.80 0.95
0.68 0.74
2.97 8.18
1.96 4.23
2.49 6.42
1.74 3.47
3.27 7.17
1.60 3.30
2.49 6.42
1.74 3.47
3.27 7.17
1.60 3.30
ns
ns
Notes
a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of BOUT6 is
20 pF, BIOT12 and B3STA12 are 30 pF.
b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer.
Loading of BOUT6 is 80 pF, BIOT12 and B3STA12 are 120 pF.
www.DataSheet4U.com
5–4 Rev. B 25 May. 98

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UG01 전자부품, 판매, 대치품
www.DataSheet4U.com
UG Series
– P1 = 0
– P2 = 5 * 0.5 * 100 * 33/16/1000 = 0.5 mW
– P3 = 52 * 16 * 33/16 * (25 + 2)/1000 = 22 mW
– P = 0 + 0.5 + 22 = 22.5 mW
D Transient energy is absorbed at the end of the line to
prevent reflections which would lead to inaccurate
ATE measurements.
Figure 4. Typical ULC Test Conditions
Typical ULC Test Conditions
For AC specification purposes, an improved output
loading scheme has been defined for TEMIC high-drive
(24 mA), high-speed ULC devices. The schematic
below (Figure 4.) describes the typical conditions for
testing these ULC devices, using the standard loading
scheme commonly available on high-end ATE.
Compared to a no-load condition, this provides the
following advantages:
D Output load is more representative of “real life”
conditions during transitions.
D.U.T.
12 mA
1.5 V
12 mA
Comp
www.DataSheet4U.com
Rev. B 25 May. 98
5–7

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