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DQ8020 데이터시트 PDF




LSI Logic에서 제조한 전자 부품 DQ8020은 전자 산업 및 응용 분야에서
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부품번호 DQ8020 기능
기능 MCC Manchester Code Converter Manual
제조업체 LSI Logic
로고 LSI Logic 로고


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DQ8020 데이터시트, 핀배열, 회로
www.DataSheet4U.com
80820200
MCCTM Manchester
Code Converter
89305
Features
s Compatible with IEEE 802.3 /Ethernet (10BASE5),
IEEE802.3/Cheapernet (10BASE2) and Ethernet
Rev. 1 Specifications
s Compatible with 8003 ELDC®, 8005 Advanced
EDLC
s Manchester Data Encoding/Decoding and
Receiver Clock Recovery with Phase Locked
Loop (PLL)
s Receiver and Collision Squelch Circuit and Noise
Rejection Filter
s Differential TRANSMIT Cable Driver
s Loopback Capability for Diagnostics and
Isolation
s Fail-Safe Watchdog Timer Circuit to Prevent
Continuous Transmission
s 20 MHz Crystal Oscillator
s Transceiver Interface High Voltage (16 V)
Short Circuit Protection
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
s Low Power CMOS Technology with Single 5V
Supply
s 20 pin DIP & PLCC Packages
Description
The SEEQ 8020 Manchester Code Converter chip pro-
vides the Manchester data encoding and decoding func-
tions of the Ethernet Local Area Network physical layer. It
interfaces to the SEEQ 8003 and 8005 Controllers and any
standard Ethernet transceiver as defined by IEEE 802.3
and Ethernet Revision 1.
Functional Block Diagram
TxEN
TxC
TxD
LPBK/
WDTD
CSN
X1
X2
RxC
RxD
COLL
WATCHDOG
TIMER
ENCODER
XTAL
CLOCK
CARRIER
SENSE
DECODER
10MHz
DETECTOR
TRANSMIT
MUX
RECEIVE
COLLISION
Figure 1. 8020 MCC Manchester Code Converter
Block Diagram.
MCC is a trademark of SEEQ Technology Inc.
wwEwD.LDCaistaarSeghiseteeret4d tUra.dceommark of SEEQ Technology Inc.
Pin Configuration
DUAL-IN LINE
TOP VIEW
Tx+
Tx–
VCC
VSS
MODE 1
Rx+
Rx–
MODE 1
GND
1
2
20 V CC
19 Tx+
LPBK/WDTD 3
18 Tx–
Rx+ 4
17 TxD
Rx–
CSN
5
6
8020
16
15
TxC
TxEN
COLL 7
14 X1
RxC 8
13 X2
RxD 9
12 COLL+
VSS 10
11 COLL–
PLASTIC LEADED CHIP CARRIER
TOP VIEW
COLL+
COLL–
3 2 1 20 19
Rx+ 4
Rx– 5
CSN 6
COLL 7
RxC 8
18 Tx–
17 TxD
16 TxC
15 TxEN
14 X1
9 10 11 12 13
MD400023/D
1




DQ8020 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
8020
TxEN Transmit Enable (Input): Transmit Enable, when
asserted, enables data to be sent to the cable. It is
asserted synchronously with TxC. TxEN goes active with
the first bit of transmission. TTL compatible.
COLL Collision (Output): When asserted, indicates to
the controller the simultaneous transmission of two or
more stations on network cable. TTL Compatible.
Transceiver Interface
Rx+ and Rx– Differential Receiver Input Pair (Input):
Differential receiver input pair which brings the encoded
receive data to the 8020. The last transition is always
positive-going to indicate the end of the frame.
COLL+ and COLL– Differential Collision Input Pair
(Input): This is a 10 MHz ± 15% differential signal from the
transceiver indicating collision. The duty cycle should not
be worse than 60%/40% — 40%/60%. The last transition
is positive-going. This signal will respond to signals in the
range of 5 MHz to 11.5 MHz. Collision signal may be
asserted if ‘MAU not available’ signal is present.
Tx+ and Tx- Differential Transmit Output Pair (Output):
Differential transmit pair which sends the encoded data to
the transceiver. The cable driver buffers are source
follower and require external 243 resistors to ground as
loading. These resistors must be rated at 1 watt to
withstand the fault conditions specified by IEEE 802.3. If
MODE 1=1, after 200 ns following the last transition, the
differential voltage is slowly reduced to zero volts in 8 µs
to limit the back swing of the coupling transformer to less
than 0.1 V.
Miscellaneous
MODE 1 (Input): This pin is used to select between AC or
DC coupling. When it is tied high or left floating, the output
drivers provide differential zero signal during idle (IEEE
802.3 specification). When pin 1 is tied low, then the
output is differentially high when idle (Ethernet Rev.1
specification).
8003
OR
8005
1
LPBK/WDTD
20 MHz
XTAL
3 MODE 1
LPBK/
WDTD
14
X1
20 pF
13
X2
20 pF
8 RxC
9 RxD
6 CSN
7 COLL
16 TxC
17 TxD
15 TxEN
SEEQ
8020
0.01 µF
Rx+ 4
5
Rx–
5 DI-A
39.2
±1%
12
DI-B
39.2
±1%
Tx+ 19
Tx– 18
3
DO-A
243 ±1%
10
DO-B
243 ±1%
1W
AUI
CABLE
COLL+ 12
11
COLL–
2 CI-A
39.2
±1%
9
CI-B
39.2
±1%
www.DataSheet4U.com
10 2
20
0.01 µF
+5
Figure 4. 8020 Interface
MD400023/D
4

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DQ8020 전자부품, 판매, 대치품
www.DataSheet4U.com
8020
A.C. Test Conditions
Output Loading TTL Output:
Differential Output:
Differential Signal Delay Time Reference Level:
Differential Output Rise and Fall Time:
RxC, TxC, X1 High and Low Time:
RxD, RxC, TxC, X1 Rise and Fall Time:
TTL Input Voltage (except X1):
X1 Input Voltage:
Differential Input Voltage:
1 TTL gate and 20 pF capacitor.
243resistor and 10 pF capacitor from each pin to VSSand
a termination 78resistor load resistor in parallel with a
27 µH inductor between the two differential output pins
50% point of swing
20% to 80% points
High time measured at 3.0V
Low time measured at 0.6V
Measured between 0.6V and 3.0 V points
0.8V to 2.0V with 10 ns rise and fall time
0.8V to 3.5V with 5 ns rise and fall time
At least ± 300 mV with rise and fall time of 10 ns measured
between –0.2V and +0.2V
20 MHz TTL Clock Input Timing TA = 0°C to 70°C; VCC = 5 V ± 5%
Symbol
Parameter
Min.
Max.
t1 X1 Cycle Time
t X1 High Time
2
t X1 Low Time
3
t X1 Rise Time
4
t5 X1 Fall Time
t5A X1 to TxC Delay Time
49.995
15
15
10
50.005
5
5
45
Unit
ns
ns
ns
ns
ns
ns
t2 t4
X1
t1 t3
t5
TxC
www.DataSheet4U.com
t 5A t 5A
Figure 12. 20 MHz TTL Clock Timing
MD400023/D
7

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