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PDF DQ80C03 Data sheet ( Hoja de datos )
| Número de pieza | DQ80C03 | |
| Descripción | Autoduplex CMOS Ethernet Data Link Controller Manual 9/96 | |
| Fabricantes | LSI Logic | |
| Logotipo |  |
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www.DataSheet4U.com
808C0C0033
AutoDUPLEXTM CMOS Ethernet
Data Link Controller
96253
Features
s Low Power CMOS Technology
s Optimized for Embedded Ethernet Applications
s Meets ANSI/IEEE 802.3 and ISO 8802-3 Standards
for Ethernet (10Base-5) Thin Net (10Base-2)
(10Base-T) and Twisted Pair
s 10 MHz Serial/Parallel Conversion
s Preamble Generation and Removal
s Automatic 32-Bit FCS (CRC) Generation and
Checking
s Collision Handling, Transmission Deferral and
Retransmission with Automatic Jam and
Backoff Functions
s Error Interrupt and Status Generation
s Available as “Ethernet Core” for Custom ASIC
Applications
s Single 5 V± 10% Power Supply
s Standard CPU and Peripheral Interface
Control Signals
s Loopback Capability for Diagnostics
s Single Phase Clock
s Inputs and Outputs TTL Compatible
Note: Check for latest Data Sheet revision
before starting any designs.
SEEQ Data Sheets are now on the Web, at
www.lsilogic.com.
This document is an LSI Logic document. Any
reference to SEEQ Technology should be
considered LSI Logic.
s Compatible with SEEQ 8003 and Provides
Additional Features
- 64 bit Multicast Filter
- Transmit Collision Counter
- Total Collision Counter
- Reports Status of “Carrier” and “SQE” During
Transmits
- Transmit No CRC Mode
- Transmit No Preamble Mode
- Transmit Packet Autopadding Mode
- Receive CRC Mode
- Receive Own Transmit Disable Mode
- Group Address Mode
- Fast Receive Discard Mode
- Full Duplex Mode
s Supports AutoDUPLEX Mode for Automatic Full
Duplex Operation— Provides 20 MBits/sec
Bandwidth for Switched Networks
s 40 Pin DIP Package, 44 Pin PLCC
Functional Block Diagram
TxD
ENCODER
INTERFACE
TRANSMIT
BYTE
COUNTER
ATTEMPT
COUNTER
COLL
TxEN
TxWR
TxRDY
TRANSMIT
BYTE
CONTROL
BACKOFF
CONTROLLER
CONTROL
REGISTER
FILE
CRC
GENERATOR
PARALLEL
/SERIAL
M
U
X
A2
A1
A0
CS
RD
WR
INT
INTERRUPT R x DC
AND
CONTROL T x RET
CdSt (0 – 7)
COMMAND/
STATUS
INTERFACE
DATA
INTERFACE
RxTxD (0 – 7)
RxTxEOF
16-BYTE
TRANSMIT
FIFO
16-BYTE
RECEIVE
FIFO
CRC
STRIPPER
RxRDY
RxRD
wwAwut.oDDUaPtLaESX his ea etratd4eUma.rck oofmSEEQ Technology Inc.
CRC
CHECKER
SERIAL
/PARALLEL
ADDRESS
CHECKER
RECEIVE
COUNTER
RECEIVE BIT
CONTROL
PLA
RESET
CSN
RxD
DECODER
INTERFACE
RECEIVE
BYTE
CONTROL
CLOCK
DRIVERS
RxC
TxC
MD400121/C
4-11
1 page  
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TRANSMIT
RECEIVE
DATA
BUFFER
DMA/
BUFFER
CONTROL
80C03
BUS
TRANSCEIVER
80C03
EDLC
8020 or 8023
MANCHESTER
CODE
CONVERTER (MCC)
COLLISION TRANSMIT RECEIVE
CPU
SYSTEM
MEMORY
TO 83C92 CMOS COAX TRANSCEIVER
83C94 CMOS TWISTED PAIR TRANSCEIVER
Figure 5. Typical Ethernet Node Configuration
Address Matching
Ethernet addresses consist of two 6-byte fields. The first
bit of the address signifies whether it is a Station Address
or a Multicast/Broadcast Address.
First Bit
0
1
Address
Station Address (Physical)
Multicast/Broadcast Address
(logical)
Address matching occurs as follows:
Station Address: All destination address bytes must
match the corresponding bytes found in the Station Ad-
dress Register. If Group Address mode is enabled, the last
4 bits of the station address are masked out during address
matching.
After computing the FCS on the first six bytes of the
address field (Destination address), the 80C03 uses bits 0
thru 5 as an address to the Multi-cast address filter
register. Bit 0 of the FCS is assumed to be where receive
data enters the FCS generation circuitry. If the corre-
sponding bit addressed in the Multicast address filter
register is a ‘1’ the 80C03 will receive the frame, otherwise
it will discard the frame. Addressing of the Multicast
address filter register occurs using bits 0 thru 2 to deter-
mine which byte is selected and bits 3 thru 5 to determine
which bit according to the following tables:
FCS Bits Byte Selected
012
000
001
010
011
111
Byte 0
Byte 1
Byte 2
Byte 3
Byte 7
FCS Bits Bit Selected
456
000
001
010
011
111
Bit 0
Bit 1
Bit 2
Bit 3
Bit 7
Multicast Address: If the first bit of the incoming address
is a 1 and the EDLC chip is programmed to accept
Multicast Addresses without using Hash filtering, the
frame is received. The 80C03 also can be programmed to
use hash filter for determining acceptance of multicast
addresses.
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MD400121/C
4-55
5 Page 
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80C03
Transmit Packet Autopad Mode
This feature automatically pads packets to be transmitted
with less than 60 bytes of data out to a minimum IEEE
802.3 standard packet length of 60 bytes excluding FCS.
Padding is done with bytes of 00 hex.
Transmit No Preamble Mode
This mode prevents the transmitter from adding a pre-
amble pattern at the beginning of data to be transmitted.
Receive Own Transmit Disable Mode
This mode prevents the 80C03 from receiving a packet if
it is also transmitting a packet.
Transmit No CRC Mode
This mode prevents the transmitter from appending trans-
mit data with an FCS.
AutoDUPLEX Mode
In this mode the transmitter will ignore carrier sense and
will not defer to it if it is ready to transmit a packet.
Receive CRC Mode
In this mode the receiver loads the 4 bytes of FCS into the
receive FIFO along with the data allowing the FCS value
to be read out.
Fast Receive Discard Mode
In this mode the receive discard signal RxDC occurs a
maximum of 400 ns after carrier sense goes low.
Pin Description
The EDLC chip has four groups of interface signals:
• Power Supply
• Data Buffer
• Encoder/Decoder
• Command/Status
Power Supply
VCC ..........................................................................+5V
VSS .....................................................................Ground
Encoder/Decoder Interface
TxC Transmit Clock (Input): 10 MHz, 50% duty cycle
transmit clock used to synchronize the transmit data from
the EDLC chip to the encoder. This clock runs continu-
ously, and is asynchronous to RxC.
TxD Transmit Data (Output): Serial Data output to the
encoder. Active HIGH.
TxEN Transmit Enable (Output): This signal is used to
activate the encoder. It becomes active when the first bit
of the Preamble is transmitted and inactive when the last
bit of the frame is transmitted. Active HIGH and cleared by
Reset.
RxC Receive Data (Input): 10 MHz, 50% duty cycle
nominal. The receive clock is used to synchronize incom-
ing data to the EDLC chip from the decoder. This clock
runs continuously, and is asynchronous to TxC.
RxD Receive Data (Input): Serial input data to the EDLC
chip from the decoder. Active HIGH.
CSN Carrier Sense (Input): Indicates traffic on the coax-
ial cable to the EDLC chip. Becomes active with the first
bit of the Preamble received, and inactive one bit time after
the last bit of the frame is received. Active HIGH.
COLL Collision (Input): Indicates transmission conten-
tion of the Ethernet cable. the Collision input is latched
internally. Sampled during transmission, Collision is set by
an active high pulse on the COLL input and automatically
reset at the end of transmission of the JAM sequence.
Data Buffer Interface
RxTxD (0-7) Receive/Transmit Data Bus (I/O): Carries
Receive/Transmit data byte from/to the EDLC chip Re-
ceive/Transmit FIFOs.
RxTxEOF Receive/Transmit End of Frame (I/O): Indi-
cates last byte of data on the Receive/Transmit Data Bus.
Effectively a ninth bit in the FIFOs with identical timing to
RxTxD (0-7). Active HIGH.
RxRDY Receive Ready (Output): Indicates that at least
one byte of received data is available in the Receive FIFO.
This signal will remain active high as long as one byte of
data remains in the Receive FIFO. When this condition no
longer exists, RxRDY will be deasserted with respect to
the leading edge of the RxRD strobe that removes the last
byte of data from the Receive FIFO. RxRD should not be
activated if RxRDY is low. Active HIGH and cleared by
Reset.
RxRD Receive Read Strobe (Input): Enables transfer of
received data from the EDLC Receive FIFO to the RxTxD
Bus. Data is valid from the EDLC Receive FIFO at the
RxTxD pins on the rising edge of this signal. This signal
should not be activated unless RxRdy is high. Active LOW.
RxDC Receive Discard (Output): Asserted when one of
the following conditions occurs, and the associated Inter-
rupt Enable bit in the Receive Command Register is reset.
(1) Receive FIFO overflow. (2) CRC Error. (3) Short Frame
Error. (4) Receive frame address nonmatch or (5) current
frame status lost because previous status was not read.
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MD400121/C
41-111
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet DQ80C03.PDF ] | |
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