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PDF MSU2031 Data sheet ( Hoja de datos )
| Número de pieza | MSU2031 | |
| Descripción | (MSU2051 / MSU2031) low working voltage 16 MHz ROM less MCU | |
| Fabricantes | Mosel Vitelic | |
| Logotipo |  |
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www.DataSheet4U.com
MOSEL VITELIC
MSU2051/U2031
Product List
MSU2031L16, low working voltage 16 MHz ROM less MCU
MSU2031S16, small sink current 16 MHz ROM less MCU
MSU2031C16, 16 MHz ROM less MCU
MSU2031C25, 25 MHz ROM less MCU
MSU2031C40, 40 MHz ROM less MCU
MSU2051L16, low working voltage 16 MHz 4 KB internal ROM MCU
MSU2051S16, small sink current 16 MHz 4 KB internal ROM MCU
MSU2051C16, 16 MHz 4 KB internal ROM MCU
MSU2051C25, 25 MHz 4 KB internal ROM MCU
MSU2051C40, 40 MHz 4 KB internal ROM MCU
Description
The MVI MSU2051 series product is an 8 - bit
single chip microcontroller. It provides hardware
features and a powerful instruction set,
necessary to make it a versatile and cost
effective controller for those applications
demand up to 32 I/O pins or need up to 64 K
byte external memory either for program or for
data or mixed.
A serial input / output port is provided for I/O
expansion, Inter - processor communications,
and full duplex UART.
Ordering Information
MSU2031ihhk
MSU2051ihh - yyyk
i: process identifier {S, L, C}.
hh: working clock in MHz {16, 25, 40}.
yyy: production code {001, ..., 999}
k: package type postfix {as below table}.
Postfix Package
blank
P
J
Q
U
dice
40L PDIP
44L PLCC
44L PQFP
44L LQFP
Pin/Pad
Configuration
page 18
page 2
page 2
page 2
page 2
Dimension
page 18
page 14
page 15
page 16
page 17
Logo Size at
Top Marking
-
5.0 x 4.2 mm
4.5 x 3.8 mm
2.8 x 2.4 mm
2.8 x 2.4 mm
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Features
Working voltage : L series at 2.7V through 4.5V
while S & C series at 4.5 V through 5.5 V
General 80C51 family compatible
64 K byte External Memory Space
4 K byte ROM
128 byte data RAM
Two 16 bit Timers/Counters
Four 8-bit I/O ports
Full duplex serial channel
Bit operation instructions
Page free jumps
8 - bit Unsigned Division
8 - bit Unsigned Multiply
BCD arithmatic
Direct Addressing
Indirect Addressing
Nested Interrupt
Two priority level interrupt
A serial I/O port
Power save modes:
Idle mode and Power down mode
Working at 16/25/40 MHz Clock
Cross Reference
M.V.I.
W.B.
Philips
L.G.
Intel
CCL. itri
Atmel
MSU2051
W78C51
80C51
GMS80C501
80C51
CIC80510
AT80C51
MSU2031
W78C31
80C31
GMS80C301
80C31
-----
AT80C31
Specifications subject to change without notice, contact your sales representatives for the most recent information.
Rev. 1.0 February 1998
1
1 page  
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MOSEL VITELIC
MSU2051/U2031
Pin Descriptions
Vss
Circuit ground potential.
V DD
+3V (or +5 V) power supply during operation.
#EA
When held at a TTL high level, the MSU2051 executes
instructions from the internal ROM when the PC is less
than 4096. When held at a TTL low level, the
MSU2051 fetches all instuctions from external Program
Memory.
PORT 0
Port 0 is an 8-bit open drain bidirectional I/O port.
It is also the multiplexed low-order address and data
bus when using external memory.
PORT 1
Port 1 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance.
XTAL 1
Input to the oscillator's high gain amplifier. A crystal or
external source can be used.
XTAL 2
Output from the oscillator's amplifier. Required when a
crystal is used.
Terms
PORT 2
Port 2 is an 8-bit quasi-bidirectional I/O port with
internal pull-up resistance. It also emit the high-order
address byte when accessing external memory.
PORT 3
Port 3 is an 8-bit quasi-bidirectinal I/O port with internal
pull-up resistance. It also contains the interrupt, timer,
serial port and #RD as well as #WR pins that are used
by various options. The output latch corresponding to a
secondary function must be programmed to one (1) for
that function to operate. The secondary functions are
assigned to the pins of port 3, as follows:
- RXD/data (P3.0). Serial port's transmitter data output
(asynchronous) or data input/output (asynchronous).
- TXD/clock (P3.1). Serial port's transmitter data
output (asynchronous) or data output (asynchronous).
- #INT0 (P3.2). Interrupt 0 input or gate control input
for counter 0.
- #INT1 (P3.3). Interrupt 1 input or gate control input
for counter 1.
- T0 (P3.4). Input to counter 0.
- T1 (P3.4). Input to counter 1.
- #WR (P3.6). The write control signal latches the data
byte from Port 0 into the External Data Memory.
- #RD (P3.7). The read control signal enables External
Data Memory to Port 0.
RES
A high on this pin for two machine cycles (24 clocks)
while the oscillator is running, resets the device. The
data in RAM is preserved when reset signals - reset
does not clear the data in RAM.
ALE
Provides Address Latch Enable output used for latching
the address into external memory during normal opera-
tion.
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#PSEN
The Program Store Enable output is a control signal that
enables the external Program Memory to the bus during
normal fetch operations.
Idle Mode
During idle mode, the CPU is stopped but below blocks
are kept functioning: clock generator, RAM, timer/
counters, serial port and interrupt block. To save power
consumption, user's software program can invoke this
mode. The on-chip data RAM retains the values during
this mode, but the processor stops executing
instructions. In Idle mode (IDL=1), the oscillator
continues to run and the interrput, and timer blocks
continue to be clocked but the clock signal is gated off
to the CPU. The activities of the CPU no longer exist
unless waiting for an interrupt request.
-An instruction that sets flag (PCON.0) causes that to be
the last instruction executed before going into the Idle
Mode.
-In the Idle Mode, the internal clock signal is gated off to
the CPU, but not to the interrupt, Timer function.
-The CPU status is entirely preserved in its:
the Stack Pointer, Program Counter, Program Status
Word, Accumulator, and all other registers maintain
their data during Idle mode.
-There are three ways to terminate the Idle Mode.
1) By interrupt
Activation of any enabled interrupt will cause flag
(PCON.0) to be cleared by hardware, termination the
Idle Mode. After the program wakes up, the PC value
will point as interrupt vector (if enable IE register) and
execute interrupt service routine then return to PC+1
address after the program wakes up.
2) By hardware reset
Since the clock oscillator is still running, the hardware
reset needs to be held active for only two machine
cycles (24 oscillator periods) to complete the reset. All
SFR and PC value will be cleared to reset value.
3) By one of CLK, DATA, PORT 2.0-2.7 transition to
low (falling edge trigger)
After the program wakes up, the PC value will be
0023h (if enable IE register) and execute interrupt
service routine and then returns to PC+1 address after
the program wakes up.
Rev. 1.0 February 1998
5
5 Page 
www.DataSheet4U.com
MOSEL VITELIC
MSU2051/U2031
Data Memory Write Cycle Timing
T12 T1 T2 T3 T4 T5 T6 T7
T8 T9 T10 T11 T12 T1 T2 T3
OSC
ALE
1
#PSEN
#WR
PORT2
PORT0
5
2
INST Float
2
A 7-A 0
3
ADDRESS A15- A 8
DATA OUT
6
4
ADDRESS
or Floa
I/O Ports Timing
T6 T7 T8 T9 T10 T11 T12 T1 T2 T3 T4 T5 T6 T7 T8
X1
inputs P0, P1
inputs P2, P3
Output by
MOV Px,Src
RxD at Serial Port
Shift Clock
(Mode 0)
sampled
sampled
current data
sampled
next data
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Rev. 1.0 February 1998
11
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet MSU2031.PDF ] | |
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