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Número de pieza | 3TN144L | |
Descripción | (3TN1xxC) MachXO Family | |
Fabricantes | Lattice Semiconductor | |
Logotipo | ||
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MachXO Family Data Sheet
Version 02.1_4W May 2006
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Lattice Semiconductor
Figure 2-1. Top View of the MachXO1200 Device1
Architecture
MachXO Family Data Sheet
PIOs Arranged into
sysIO Banks
sysMEM Embedded
Block RAM (EBR)
Programmable
Functional Units
with RAM (PFUs)
Programmable
Functional Units
without RAM (PFFs)
sysCLOCK
PLL
JTAG Port
1. Top view of the MachXO2280 device is similar but with higher LUT count, two PLLs, and three EBR blocks.
Figure 2-2. Top View of the MachXO640 Device
PIOs Arranged into
sysIO Banks
Programmable
Function Units
without RAM (PFFs)
Programmable
Function Units
with RAM (PFUs)
JTAG Port
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Lattice Semiconductor
Architecture
MachXO Family Data Sheet
Figure 2-8. Primary Clocks for MachXO1200 and MachXO2280 Devices
Up to 9
4
Up to 6
Primary Clock 0
16:1
Primary Clock 1
16:1
Primary Clock 2
16:1
Primary Clock 3
16:1
Routing Clock PLL
Pads Outputs
Four secondary clocks are generated from four 16:1 muxes as shown in Figure 2-9. Four of the secondary clock
sources come from dual function clock pins and 12 come from internal routing.
Figure 2-9. Secondary Clocks for MachXO Devices
12 4
16:1
16:1
Secondary (Control)
Clocks
16:1
Routing Clock
Pads
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16:1
2-8
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet 3TN144L.PDF ] |
Número de pieza | Descripción | Fabricantes |
3TN144C | (3TN1xxC) MachXO Family | Lattice Semiconductor |
3TN144C4W | (3TN1xxC) MachXO Family | Lattice Semiconductor |
3TN144L | (3TN1xxC) MachXO Family | Lattice Semiconductor |
3TN144L4W | (3TN1xxC) MachXO Family | Lattice Semiconductor |
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