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A1020B-xxxx 데이터시트 PDF




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A1020B-xxxx 데이터시트, 핀배열, 회로
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v3.0
RadTolerant FPGAs
Features
General Characteristics
• Tested Total Ionizing Dose (TID) Survivability Level
• No Single Event Latch-up Below a Minimum LET
Threshold of 80 MeV-cm2/mg for All RT Devices
• Packages: 84-Pin, 132-Pin, 172-Pin, 196-Pin, and 256-Pin
Ceramic Quad Flat Pack
• Offered as Class B and E-Flow (Actel Space Level Flow)
• QML Certified Devices
• 100% Military Temperature Tested (–55°C to +125°C)
High Density and Performance
• 4,000 to 20,000 Logic Equivalent Gates
• 2,000 to 10,000 ASIC Equivalent Gates
• Up to 85 MHz Internal Performance
• Up to 60 MHz System Performance
• Up to 228 User I/Os
• Up to Four Fast, Low-Skew Clock Networks
Easy Logic Integration
• Non-Volatile, User Programmable
• Pin-Compatible Commercial Devices Available for
Prototyping
• Highly Predictable Performance with 100% Automatic
Place and Route
• 100% Resource Utilization with 100% Pin-Locking
• Secure Programming Technology Prevents Reverse
Engineering and Design Theft
• Permanently Programmed for Operation on Power-Up
• Unique In-System Diagnostic and Verification Capability
with Silicon Explorer
General Description
Actel builds the most reliable field programmable gate arrays
(FPGAs) in the industry, with overall antifuse reliability
ratings of less than 10 failures-in-time (FITs), corresponding
to a useful life of more than 40 years. Actel FPGAs are
production-proven, with more than five million devices
shipped and more than one trillion antifuses manufactured.
Actel devices are fully tested prior to shipment, with an
out-going defect level of only 122 ppm (further reliability data
is available in the Actel Device Reliability Report at
http://www.actel.com/hirel).
Additionally, the programmable architecture of these devices
offers high performance, design flexibility, and fast and
inexpensive prototyping—all without the expense of test
vectors, NRE charges, long lead times, and schedule and cost
penalties for design refinements.
Product Family Profile
Device
Capacity
System Gates
Logic Gates
ASIC Equivalent Gates
PLD Equivalent Gates
mTTL Equivalent Package
o20-Pin PAL Equivalent Packages
.cLogic Modules
US-Modules
t4C-Modules
eUser I/Os (Maximum)
hePerformance
SSystem Speed (Maximum)
taPackages (by Pin Count)
a CQFP
w.D January 2000
ww © 2000 Actel Corporation
RT1020
6,000
4,000
2,000
5,000
50
20
547
N/A
547
69
20 MHz
84
RT1280A
24,000
16,000
8.000
20,000
200
80
1,232
624
608
140
40 MHz
172
RT1425A
7,500
5,000
2,500
6,250
60
25
310
160
150
100
60 MHz
132
RT1460A
18,000
12,000
6,000
15.000
150
60
848
432
416
168
60 MHz
196
RT14100A
30,000
20,000
10,000
25,000
250
100
1,377
697
680
228
60 MHz
256
1




A1020B-xxxx pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Product Plan
Speed Grade
Application
Std –1*
CMB E
ACT 1
RT1020 Device
84-Pin Ceramic Quad Flat Pack (CQFP)
A1020B Device (Prototyping Use)
— ——
84-Pin Ceramic Quad Flat Pack (CQFP)
ACT 2
RT1280A Device
172-Pin Ceramic Quad Flat Pack (CQFP)
A1280A Device (Prototyping Use)
——
172-Pin Ceramic Quad Flat Pack (CQFP)
ACT 3
RT1425A Device
132-Pin Ceramic Quad Flat Pack (CQFP)
A1425A Device (Prototyping Use)
——
132-Pin Ceramic Quad Flat Pack (CQFP)
RT1460A Device
196-Pin Ceramic Quad Flat Pack (CQFP)
A1460A Device (Prototyping Use)
——
196-Pin Ceramic Quad Flat Pack (CQFP)
RT14100A Device
256-Pin Ceramic Quad Flat Pack (CQFP)
A14100A Device (Prototyping Use)
——
256-Pin Ceramic Quad Flat Pack (CQFP)
Contact your Actel sales representative for product availability.
Applications: C = Commercial
M = Military
B = MIL-STD-883
Availability: = Available
— = Not Planned
E = Extended Flow
*Speed Grade: –1 = Approx. 15% faster than Standard
Device Resources
mFPGA Device Type
Logic
Modules
Gate Array
Equivalent
Gates
CQFP
84-Pin
.coRT1020/A1020B
547 2,000
URT1280A/A1280A
1,232
8,000
t4RT1425A/A1425A
310 2,500
eRT1460A/A1460A
848 6,000
heRT14100A/A14100A
1,377
10,000
SPackage Definitions: CQFP = Ceramic Quad Flat Pack
ta(Contact your Actel sales representative for product availability.)
69
www.Da4
CQFP
132-Pin
100
User I/Os
CQFP
172-Pin
140
CQFP
196-Pin
168
CQFP
256-Pin
228

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A1020B-xxxx 전자부품, 판매, 대치품
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RadTolerant FPGAs
Vertical Routing
Another set of routing tracks run vertically through the
module. There are three types of vertical tracks, input,
output, and long, that can be divided into one or more
segments. Each segment in an input track is dedicated to the
input of a particular module. Each segment in an output track
is dedicated to the output of a particular module. Long
segments are uncommitted and can be assigned during
routing. Each output segment spans four channels (two above
and two below), except near the top and bottom of the array
where edge effects occur. Long vertical tracks contain either
one or two segments. An example of vertical routing tracks
and segments is shown in Figure 5.
Segmented
Horizontal
Routing
Tracks
Logic
Modules
Antifuse Structures
An antifuse is a “normally open” structure as opposed to the
normally closed fuse structure used in PROMs or PALs. The
use of antifuses to implement a programmable logic device
results in highly testable structures, as well as efficient
programming algorithms. The structure is highly testable
because there are no pre-existing connections, enabling
temporary connections to be made using pass transistors.
These temporary connections can isolate individual antifuses
to be programmed, as well as isolate individual circuit
structures to be tested. This can be done both before and
after programming. For example, all metal tracks can be
tested for continuity and shorts between adjacent tracks, and
the functionality of all logic modules can be verified.
Antifuses
Vertical Routing Tracks
Figure 5 • Routing Structure
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관련 데이터시트

부품번호상세설명 및 기능제조사
A1020B-xxxx

FPGAs

Actel
Actel
A1020B-xxxx

(A1010B / A1020B) FPGAs

Actel Corporation
Actel Corporation

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