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CS4812 데이터시트 PDF




Cirrus Logic에서 제조한 전자 부품 CS4812은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


PDF 형식의 CS4812 자료 제공

부품번호 CS4812 기능
기능 Fixed Function Multi-Effects Audio Processor
제조업체 Cirrus Logic
로고 Cirrus Logic 로고


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CS4812 데이터시트, 핀배열, 회로
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CS4812
Fixed Function Multi-Effects Audio Processor
Features
l DSP for embedded reverb/effects
applications
– 24-bit Audio Processing Engine
– No External RAM required
– Two 24-bit ∆Σ ADCs with 100 dB Dyn. Range
– Two 24-bit ∆Σ DACs with 100 dB Dyn. Range
l Mono Guitar or Mixer Effects firmware
included
l Real time parameter control via messaging
protocol
l Serial Control Port for microcontroller
interface
l Single +5V supply operation
l 100-pin Metric Quad Flat Package (MQFP)
ORDERING INFO
CS4812-KM -10 to +70°C 100-pin MQFP
CDB4812 Electric Guitar Effects w/
Parameter Controls.
Description
The CS4812 is a complete audio effects processing
system on a chip. This device includes a proprietary 24-
bit audio processing engine with considerable on-chip
RAM, two ADCs and two DACs. A full-featured serial
control port allows interfacing to an external host
microcontroller. Other features such as single +5V
operation simplify system design.
The CS4812, combined with Crystal effects firmware, is
the ideal solution for a variety of effects processing
applications where user parameter control is desired.
The Crystal effects firmware provides a messaging
protocol for the serial control port that allows an external
microcontroller to have real-time parameter control over
the audio effects. The complete processor and effects
solution may be evaluated with the CDB4812
demonstration board. The CDB4812 demonstrates a
host of mono electric guitar effects including a digital
spring reverb, delay, chorus, flange and tremolo with
parameter adjustment capability. Please refer to AN195
for more information on application firmware for the
CS4812.
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ataSP.O. Box 17847, Austin, Texas 78760
.D(512) 445 7222 FAX: (512) 445 7581
www http://www.cirrus.com

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This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Copyright Cirrus Logic, Inc. 2001
(All Rights Reserved)
JUL ‘01
DS291PP3
1




CS4812 pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
CS4812
1. CHARACTERISTICS AND SPECIFICATIONS
ADC CHARACTERISTICS (TA = 25°C; VA, VD = + 5V; -1 dB Full Scale Input Sine wave,
997 Hz; Fs = 48 kHz; XTI = 12.288 MHz (PLL disabled). Measurement Bandwidth is 20 Hz to 20 kHz.)
Parameters
Symbol Min Typ Max Units
Analog Input Characteristics
ADC Conversion
Stereo Audio channels
16 - 24 Bits
Dynamic Range
(A weighted, Note 5)
(unweighted, Note 5)
93 100
90 97
-
-
dB
dB
Total Harmonic Distortion + Noise
(PLL enabled)
(Note 1,5) THD+N - -92 -87 dB
(Note 1,2,5)
- -92 -
Interchannel Isolation
- 90 -
dB
Interchannel Gain Mismatch
- 0.1 -
dB
Offset Error (with high pass filter enabled)
(Note 6)
- - 0 LSB
Full Scale Input Voltage (Differential)
Gain Drift
(Note 2)
1.9 2.0 2.1 Vrms
- 100 - ppm/°C
Input Resistance
10 - - k
Input Capacitance
- - 15 pF
CMOUT Output Voltage
- 2.3 -
V
Common Mode Rejection Ratio
(Note 2) CMRR
60
dB
Group Delay (Fs = Output Sample Rate)
Group Delay Variation vs. Frequency
High Pass Filter Characteristics
(Note 4)
tgd
tgd
- 15/Fs -
- -0
s
µs
Frequency Response
-3dB (Note 3)
-0.14dB (Note 3)
- 3.7 -
- 20 -
Hz
Hz
Phase Deviation
@ 20 Hz (Note 3)
- 10 - Degree
Passband Ripple
- - 0 dB
Notes: 1. Referenced to typical full-scale differential input voltage (2 Vrms).
2. Bench tested only.
3. Filter characteristics scale with output sample rate.
4. Group delay for Fs = 48 kHz, tgd = 15/48 kHz = 313 µs.
5. Measured using differential analog input circuit, see Figure 10.
6. Filter Response is not tested but guaranteed by design.
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CS4812 전자부품, 판매, 대치품
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CS4812
SWITCHING CHARACTERISTICS - CONTROL PORT - SPI SLAVE
(TA = 25 °C; VA, VD = 5 V; Inputs: Logic 0 = DGND, Logic 1 = VD, CL = 30 pF)
Parameter
Symbol
Min
Max
SPI Slave Mode (SPI/I2C = 0, SCPM/S = 0, Note 14)
CCLK Clock Frequency
CCLK Low Time
CCLK High Time
Rise Time of Both CDIN and CCLK Lines
Fall Time of Both CDIN and CCLK Lines
Setup Time CDIN to CCLK Rising
Hold Time CCLK Rising to CDIN
(Note 11)
Time from CCLK edge to CDOUT Valid
(Note 12)
Rise Time for CDOUT
Fall Time for CDOUT
CS Falling to CCLK Rising
Time from CCLK Falling to CS Rising
High Time Between Active CS
Time from CCLK Rising to REQ Rising
(Note 13)
Rise Time for REQ
Fall Time for REQ
fsck
tscl
tsch
tr
tf
tcdisu
tcdih
tscdov
tcdor
tcdof
tcss
tsccsh
tcsht
tscrh
trr
trf
-6
66 -
66 -
- 100
- 100
40 -
15 -
- 45
- 25
- 25
20 -
0-
1-
- 2*DSPCLK+10
- 100
- 100
Notes: 11. Data must be held for sufficient time to bridge 100 ns transition time of CCLK.
12. CDOUT should NOT be sampled during this time period.
13. DSPCLK frequency is twice the DSP instruction rate.
14. Timing is guaranteed by characterization. Production test guarantees functionality.
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ns
ns
ns
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