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PDF MS6260 Data sheet ( Hoja de datos )
| Número de pieza | MS6260 | |
| Descripción | Gain and Attenuation Volume Controller IC | |
| Fabricantes | Mosa Electronics | |
| Logotipo |  |
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MOSA
MS6260
Gain And Attenuation Volume Controller IC
Gain and Attenuation Volume Controller IC
One Set of Stereo Input, Low voltage
Gain and Attenuation 15~-79dB, Good PSRR
FEATURES
‧Operation range: 2.7V~5.5V
‧Low power consumption
‧Gain/Attenuation: 15dB to –79dB at 1dB/step
‧Good PSRR and low pop noise
‧Housed in 10 pin MSOP package
‧I2C interface
APPLICATIONS
‧Multimedia system
‧Hi-Fi audio system
‧MP3, PDA
DESCRIPTION
The MS6260 is the stereo audio volume controller IC. It uses CMOS technology specially for the low voltage
application with low noise, rail-to-rail output. The MS6260 provide an I2C control interface with gain / attenuation
range of 15dB to –79dB, 1dB/step. The excellent power supply ripple reject is a good for audio system. The initial
condition is set to be maximum attenuation –79dB and mute on mode when power on.
PIN CONFIGURATION
Symbol
A.O.
L-IN
L-OUT
VSS
SDA
SCL
VDD
R-OUT
R-IN
VREF
Pin Description
1 Address option *
2 Left channel input
3 Left channel output
4 Ground
5 I2C data input
6 I2C clock input
7 Positive supply voltage
8 Right channel output
9 Right channel input
10 Reference voltage = 1/2VDD
A.O. 1
L-IN 2
L-OUT 3
VSS 4
SDA 5
Note: 1. Pin 1 is set to Lo or open , the address code is 88H (10001000B).
2. Pin 1 is set to Hi , the address code is 8CH (10001100B).
3. The VREF connects a capacitor to Vss.
MS6260
10 VREF
9 R-IN
8 R-OUT
7 VDD
6 SCL
REV 1
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MOSA
MS6260
Gain And Attenuation Volume Controller IC
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=5V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=3.3V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
CAP=22uF
CAP=10uF
CAP=2.2uF
VDD=2.7V
VRR=-20dBV
FREQUENCY (Hz)
PSRR vs. frequency
I2C BUS DESCRIPTION
Start and stop conditions
A start condition is activated when the SCL is set to HIGH and SDA shifts from HIGH to LOW state. The stop
condition is activated when SCL is set to HIGH and SDA shifts from LOW to HIGH state. Please refer to the timing
diagram below.
SCL
SDA
Start
SCL : Serial Clock Line, SDA : Serial Data Line
Stop
Data validity
A data on the SDA line is considered valid and stable only when the SCL signal is in HIGH state. The HIGH and
LOW states of the SDA line can only change when the SCL signal is LOW. Please refer to the figure below.
SDA
SCL
Data line Data
stable, change
Data valid allowed
Byte format
Every byte transmitted to the SDA line consists of 8 bits. Each byte must be followed by an acknowledge bit.
The MSB is transmitted first.
REV 1
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MOSA
EXTERNAL DIMENSIONS
MSOP10 package
MS6260
Gain And Attenuation Volume Controller IC
HE
A A2
A1
D
eB
Symbol Dimension in mm Dimension in inch
Min Max Min Max
A 0.81 1.12 0.032 0.044
A1 0.05 0.15 0.002 0.006
A2 0.76 0.97 0.030 0.038
B 0.15 0.20 0.006 0.012
C 0.13 0.23 0.005 0.009
D 2.90 3.10 0.114 0.122
H 4.70 5.10 0.185 0.201
E 2.90 3.10 0.114 0.122
e 0.50
0.0197
L 0.40 0.66 0.016 0.026
L
C
TAPE AND REEL (Unit : mm)
0.30 0.05
2.0 0.05
4.0
0.3R MAX
5.4
2.0 1.7
3.0
3.6
6.9
1.5+0.1/-0.0 DIA
8.0
1.5 MIN
1.75
5.5 0.05
12.0 0.3
0.5 Radius Typical
REV 1
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet MS6260.PDF ] | |
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