PDF ICS9FG107 Data sheet ( Hoja de datos )

Número de pieza	ICS9FG107
Descripción	Programmable FTG for Differential CPU
Fabricantes	Integrated Circuit Systems
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No Preview Available ! www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG107 Programmable FTG for Differential CPU, PCI Express* & SATA Clocks Recommended Application: Pin Configuration Frequency Timing Generator for Differential CPU, PCI Express & SATA clocks XIN/CLKIN 1 X2 2 48 VDDA 47 GNDA Features: VDD 3 46 IREF • Generates common CPU/PCI Express frequencies from 14.318 MHz or 25 MHz • Crystal or reference input • 7 - 0.7V current-mode differential output pairs • 3 - 33MHz PCI outputs • 1 - REFOUT • Supports Serial-ATA at 100 MHz • Two spread spectrum modes: 0 to -0.5 downspread and +/-0.25% centerspread • Unused inputs may be disabled in either driven or Hi-Z state for power management. GND 4 FS2/REFOUT 5 GND 6 FS0/PCICLK_F 7 PCICLK0 8 PCICLK1 9 VDD 10 *OE_6 11 DIF_6 12 DIF_6# 13 45 DWNSPRD# 44 *FS1 43 OE_0 42 DIF_0 41 DIF_0# 40 VDD 39 DIF_1 38 DIF_1# 37 OE_1 36 VDD VDD 14 35 GND Key Specifications: GND 15 34 OE_2 • Output cycle-to-cycle jitter for DIF outputs < 50 ps (<85ps @ 266 MHz) • Output to output skew for DIF outputs < 85 ps • +/-300 ppm frequency accuracy on output clocks *OE_5 16 DIF_5 17 DIF_5# 18 VDD 19 33 DIF_2 32 DIF_2# 31 VDD 30 DIF_3 DIF_4 20 29 DIF_3# Frequency Select Table SEL14M_25M# (FS3) FS2 FS1 FS0 OUTPUT(MHz) 0 000 100.00 0 001 125.00 0 010 133.33 0 011 166.67 0 100 200.00 DIF_4# 21 OE_4 22 SDATA 23 SCLK 24 28 OE_3 27 SEL14M_25M# 26 SPREAD 25 DIF_STOP# Notes: 48-pin SSOP & TSSOP Pins preceeded by * have 120 Kohm pull DOWN resistors Pins preceeded by ** have 120 Kohm pull UP resistors 0 101 266.66 0 110 333.33 0 111 400.00 1 000 100.00 1 001 125.00 1 010 133.33 1 011 166.67 1 100 200.00 1 101 266.66 1 110 333.33 1 111 400.00 0863C—11/22/04 *Other names and brands may be claimed as the property of others. 1 page www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS9FG107 Absolute Max Symbol Parameter VDD_A 3.3V Core Supply Voltage VDD_In 3.3V Logic Input Supply Voltage Ts Tambient Tcase ESD prot Storage Temperature Ambient Operating Temp Case Temperature Input ESD protection human body model Min GND - 0.5 -65 0 2000 Max VDD + 0.5V VDD + 0.5V 150 70 115 Units V V °C °C °C V Electrical Characteristics - Input/Supply/Common Output Parameters TA = 0 - 70°C; Supply Voltage VDD = 3.3 V +/-5% PARAMETER SYMBOL CONDITIONS MIN TYP Input High Voltage Input Low Voltage Input High Current Input Low Current VIH 3.3 V +/-5% 2 VIL 3.3 V +/-5% VSS - 0.3 IIH VIN = VDD -5 IIL1 VIN = 0 V; Inputs with no pull- up resistors -5 IIL2 VIN = 0 V; Inputs with pull-up resistors -200 Operating Supply Current IDD3.3OP Input Frequency3 Pin Inductance1 Input/Output Capacitance1 Clk Stabilization1,2 Modulation Frequency DIF output enable Fi Lpin CIN COUT TSTAB fMOD tDIFOE Full Active, CL = Full load; f = 400 MHz Full Active, CL = Full load; f = 100 MHz VDD = 3.3 V Logic Inputs Output pin capacitance From VDD Power-Up and after input clock stabilization to 1st clock Triangular Modulation DIF output enable after DIF_Stop# de-assertion 14 1.5 30 MAX UNITS NOTES VDD + 0.3 0.8 V V 5 uA uA uA 250 mA 200 mA 25 MHz 3 7 nH 1 5 pF 1 6 pF 1 1.8 ms 1,2 40 kHz 1 10 ns 1 Input Rise and Fall times tR/tF 20% to 80% of VDD 5 ns 1Guaranteed by design and characterization, not 100% tested in production. 2See timing diagrams for timing requirements. 3 Input frequency should be measured at the REFOUT pin and tuned to ideal 14.31818MHz or 25 MHz to meet ppm frequency accuracy on PLL outputs. 1 0863C—11/22/04 5 5 Page www.DataSheet4U.com Integrated Circuit Systems, Inc. I2C Table: Byte Count Register Byte 6 Pin # Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 - - - - - - - - BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 Control Function Writing to this register will configure how many bytes will be read back, default is 07 = 7 bytes. Type RW RW RW RW RW RW RW RW 0 - - - - - - - - ICS9FG107 1 PWD -0 -0 -0 -0 -0 -1 -1 -1 0863C—11/22/04 11 11 Page

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