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ARM946E-S PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ARM946E-S
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ARM946E-S 데이터시트, 핀배열, 회로
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ARM946E-S
Revision: r1p1
Technical Reference Manual
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI 0201C




ARM946E-S pdf, 반도체, 판매, 대치품
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Contents
Chapter 5
Chapter 6
Chapter 7
Chapter 8
Chapter 9
4.2 Memory regions .......................................................................................... 4-3
4.3 Overlapping regions ................................................................................... 4-6
Tightly-Coupled Memory Interface
5.1 ARM946E-S TCM interface description ...................................................... 5-2
5.2 Using CP15 Control Register ..................................................................... 5-3
5.3 Enabling the Instruction TCM during soft reset .......................................... 5-7
5.4 Data TCM accesses ................................................................................... 5-8
5.5 Instruction TCM accesses .......................................................................... 5-9
Bus Interface Unit and Write Buffer
6.1 About the BIU and write buffer ................................................................... 6-2
6.2 AHB bus master interface ........................................................................... 6-3
6.3 Noncached Thumb instruction fetches ..................................................... 6-10
6.4 AHB clocking ............................................................................................ 6-11
6.5 The write buffer ......................................................................................... 6-14
Coprocessor Interface
7.1 About the coprocessor interface ................................................................. 7-2
7.2 Coprocessor interface signals .................................................................... 7-3
7.3 LDC/STC .................................................................................................. 7-11
7.4 MCR/MRC ................................................................................................ 7-13
7.5 Interlocked MCR ....................................................................................... 7-14
7.6 CDP .......................................................................................................... 7-15
7.7 Privileged instructions ............................................................................... 7-16
7.8 Busy-waiting and interrupts ...................................................................... 7-17
ETM Interface
8.1 About the ETM interface ............................................................................. 8-2
8.2 Enabling the ETM interface ........................................................................ 8-3
8.3 ARM946E-S trace support features ............................................................ 8-4
Debug Support
9.1 About the debug interface .......................................................................... 9-2
9.2 Debug systems ........................................................................................... 9-4
9.3 The JTAG state machine ............................................................................ 9-7
9.4 Scan chains .............................................................................................. 9-12
9.5 Debug access to the caches .................................................................... 9-18
9.6 Debug interface signals ............................................................................ 9-20
9.7 Determining the core and system state .................................................... 9-25
9.8 Overview of EmbeddedICE-RT ................................................................ 9-26
9.9 Disabling EmbeddedICE-RT .................................................................... 9-28
9.10 The debug communication channel .......................................................... 9-29
9.11 Monitor mode debugging .......................................................................... 9-33
iv
Copyright © 2001-2003 ARM Limited. All rights reserved.
ARM DDI 0201C

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ARM946E-S 전자부품, 판매, 대치품
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List of Tables
ARM946E-S Technical Reference Manual
Table 1-1
Table 2-1
Table 2-2
Table 2-3
Table 2-4
Table 2-5
Table 2-6
Table 2-7
Table 2-8
Table 2-9
Table 2-10
Table 2-11
Table 2-12
Table 2-13
Table 2-14
Table 2-15
Table 2-16
Table 2-17
Table 2-18
Table 2-19
Table 2-20
Table 2-21
ARM DDI 0201C
Change history .............................................................................................................. ii
Location of block descriptions ................................................................................... 1-4
CP15 register map .................................................................................................... 2-5
CP15 terms and abbreviations .................................................................................. 2-6
Register 0, ID code ................................................................................................... 2-8
Cache Type Register format ..................................................................................... 2-8
Cache size encoding ................................................................................................. 2-9
Cache associativity encoding .................................................................................. 2-10
Tightly-coupled Memory Size Register ................................................................... 2-11
Memory size field .................................................................................................... 2-11
Register 1, Control Register .................................................................................... 2-12
Programming instruction and data cachable bits .................................................... 2-16
Programming data bufferable bits ........................................................................... 2-17
Programming instruction and data access permission bits (extended) ................... 2-17
Access permission encoding (extended) ............................................................... 2-18
Instruction and data access permission bits (standard) .......................................... 2-19
Access permission encoding (standard) ................................................................. 2-19
Accessing Protection Region Base and Size Registers .......................................... 2-20
Protection Region Base and Size Register format .................................................. 2-21
Region size encoding .............................................................................................. 2-21
Cache operations .................................................................................................... 2-23
Index fields for supported cache sizes .................................................................... 2-24
Lockdown Register format ...................................................................................... 2-26
Copyright © 2001-2003 ARM Limited. All rights reserved.
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