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ARM946E-S PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 ARM946E-S
기능 Microprocessor Core
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ARM946E-S 데이터시트, 핀배열, 회로
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Technical
Manual
ARM946E-S
Microprocessor Core
with Cache
June 2001
®




ARM946E-S pdf, 반도체, 판매, 대치품
www.DataSheet4U.com
Chapter 6, Tightly Coupled SRAM, describes the requirements and
operation of the tightly coupled SRAM.
Chapter 7, Bus Interface Unit and Write Buffer, describes the
operation of the Bus Interface Unit and write buffer.
Chapter 8, External Coprocessor Interface, describes the coprocessor
interface and the operation of common coprocessor instructions.
Chapter 9, Debug Interface, describes the debug support for the
ARM946E-S and the EmbeddedICE-RT logic.
Chapter 10, ETM Interface, describes the ETM interface, including
details of how to enable the interface.
Chapter 11, Test Support, describes the test methodology used for the
ARM946E-S synthesized logic and tightly coupled SRAM.
Appendix A, AC Parameters, describes the timing parameters applicable
to the ARM946E-S.
Related Publications
ARM Architecture Reference Manual available from ARM Ltd. as
document No. ARM DDI 0100.
ARM9E-S Technical Reference Manual available from ARM Ltd. as
document No.ARM DDI 0165.
AMBA Specification (Rev 2.0) available from ARM Ltd. as document No.
ARM IHI 0011.
Embedded Trace Macrocell Specification (Rev 1.0) available from ARM
Ltd. as document number IHI 0014E.
Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990
Conventions Used in This Manual
The first time a word or phrase is defined in this manual, it is italicized.
iv Preface
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.

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ARM946E-S 전자부품, 판매, 대치품
www.DataSheet4U.com
Contents
Chapter 1
Chapter 2
Introduction
1.1 About the ARM946E-S
1.2 Microprocessor Block Diagram
1.2.1 ARM9E-S Processor Core
1.2.2 System Controller
1.2.3 CP15 System Control Coprocessor
1.2.4 Data and Instruction Caches and Control
1.2.5 Protection Unit
1.2.6 Instruction and Data SRAMs
1.2.7 AHB Interface Unit and Write Buffer
1.2.8 External Coprocessor Interface
1.2.9 JTAG and Debug Interface Port
1.2.10 Embedded Trace Module Interface
1.3 CoreWare® Program
Signal Descriptions
2.1 Signal Properties and Requirements
2.2 Clock Interface Signals
2.3 AHB Signals
2.4 Instruction RAM Signals
2.5 Data RAM Signals
2.6 Instruction Cache Signals
2.7 Data Cache Signals
2.8 Coprocessor Interface Signals
2.9 Debug Signals
2.10 JTAG Signals
2.11 Miscellaneous Signals
2.12 ETM Interface Signals
2.13 ATPG Scan Control Signals
1-1
1-2
1-4
1-4
1-4
1-5
1-5
1-5
1-5
1-6
1-6
1-6
1-6
2-1
2-5
2-5
2-8
2-10
2-11
2-15
2-20
2-22
2-24
2-25
2-25
2-30
ARM946E-S Microprocessor Core with Cache Technical Manual
Copyright © 2000–2001 by LSI Logic Corporation. All rights reserved.
vii

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ARM946E-S

Manual

ARM
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ARM946E-S

Microprocessor Core

LSI Logic Corporation
LSI Logic Corporation

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