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E500CORERM PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 E500CORERM
기능 PowerPC e500 Core Family
제조업체 Freescale
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E500CORERM 데이터시트, 핀배열, 회로
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PowerPC™ e500 Core
Family Reference Manual
Supports
e500v1
e500v2
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E500CORERM
Rev. 1, 4/2005
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E500CORERM pdf, 반도체, 판매, 대치품
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I Part I—e500 Core
1 Core Complex Overview
2 Register Model
3 Instruction Model
4 1 Execution Timing
5 Interrupts and Exceptions
6 Power Management
7 Performance Monitor
8 Debug Support
II Part II—e500 Core Complex
9 Timer Facilities
10 Auxiliarwy Pwrocwess.inDg Uanittsa(ASPUhs)eet4U.com
11 L1 Caches
12 Memory Management Units
13 Core Complex Bus (CCB)
A Appendix A—Programming Examples
B Appendix B—Guidelines for 32-Bit Book E
C Appendix C—Simplified Mnemonics for PowerPC Instructions
D Appendix D—Opcode Listings
E Appendix E—Revision History
IND Index
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E500CORERM 전자부품, 판매, 대치품
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Contents
Paragraph
Number
Title
Page
Number
2.6
2.6.1
2.6.2
2.6.3
2.6.4
2.6.5
2.6.6
2.6.6.1
2.7
2.7.1
2.7.1.1
2.7.1.2
2.7.1.3
2.7.1.4
2.7.1.5
2.7.1.6
2.7.2
2.7.2.1
2.7.2.2
2.7.2.3
2.7.2.4
2.8
2.9
2.9.1
2.9.2
2.9.3
2.10
2.10.1
2.10.2
2.11
2.11.1
2.11.2
2.11.3
2.11.4
2.12
2.12.1
2.12.2
2.12.3
Timer Registers .............................................................................................................. 2-14
Timer Control Register (TCR)................................................................................... 2-15
Timer Status Register (TSR)...................................................................................... 2-16
Time Base (TBU and TBL) ....................................................................................... 2-16
Decrementer Register (DEC)..................................................................................... 2-16
Decrementer Auto-Reload Register (DECAR).......................................................... 2-16
Alternate Time Base Registers (ATBL and ATBU)................................................... 2-16
Alternate Time Base Upper (ATBU) ..................................................................... 2-17
Interrupt Registers.......................................................................................................... 2-17
Interrupt Registers Defined by Book E...................................................................... 2-18
Save/Restore Register 0/1 (SRR0 and SRR1) ....................................................... 2-18
Critical Save/Restore Register 0/1 (CSRR0 and CSRR1) ..................................... 2-18
Data Exception Address Register (DEAR)............................................................ 2-18
Interrupt Vector Prefix Register (IVPR) ................................................................ 2-19
Interrupt Vector Offset Registers (IVORs) ............................................................ 2-19
Exception Syndrome Register (ESR) .................................................................... 2-20
e500-Specific Interrupt Registers .............................................................................. 2-22
Machine Check Save/Restore Register 0 (MCSRR0) ........................................... 2-22
www.DataSheet4U.comMachine Check Save/Restore Register 1 (MCSRR1) ........................................... 2-22
Machine Check Address Register (MCAR) .......................................................... 2-22
Machine Check Syndrome Register (MCSR)........................................................ 2-23
Software-Use SPRs (SPRG0–SPRG7 and USPRG0) ................................................... 2-24
Branch Target Buffer (BTB) Registers .......................................................................... 2-24
Branch Buffer Entry Address Register (BBEAR) ..................................................... 2-25
Branch Buffer Target Address Register (BBTAR) .................................................... 2-25
Branch Unit Control and Status Register (BUCSR) .................................................. 2-26
Hardware Implementation-Dependent Registers........................................................... 2-27
Hardware Implementation-Dependent Register 0 (HID0)......................................... 2-27
Hardware Implementation-Dependent Register 1 (HID1)......................................... 2-29
L1 Cache Configuration Registers................................................................................. 2-31
L1 Cache Control and Status Register 0 (L1CSR0) .................................................. 2-31
L1 Cache Control and Status Register 1 (L1CSR1) .................................................. 2-33
L1 Cache Configuration Register 0 (L1CFG0) ......................................................... 2-34
L1 Cache Configuration Register 1 (L1CFG1) ......................................................... 2-35
MMU Registers.............................................................................................................. 2-35
Process ID Registers (PID0–PID2)............................................................................ 2-36
MMU Control and Status Register 0 (MMUCSR0) .................................................. 2-36
MMU Configuration Register (MMUCFG) .............................................................. 2-37
Freescale Semiconductor
PowerPC e500 Core Family Reference Manual, Rev. 1
vii
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E500CORERM

PowerPC e500 Core Family

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