|
|
Número de pieza | E500CORERM | |
Descripción | PowerPC e500 Core Family | |
Fabricantes | Freescale | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de E500CORERM (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
No Preview Available ! www.DataSheet4U.com
PowerPC™ e500 Core
Family Reference Manual
Supports
e500v1
e500v2
www.DataSheet4U.com
E500CORERM
Rev. 1, 4/2005
www.DataSheet4U.com
1 page www.DataSheet4U.com
Paragraph
Number
Contents
Title
Page
Number
Co nt en ts
About This Book
Audience ....................................................................................................................... xxxii
Organization.................................................................................................................. xxxii
Suggested Reading....................................................................................................... xxxiii
General Information............................................................................................. xxxiii
Related Documentation ....................................................................................... xxxiv
Conventions ................................................................................................................. xxxiv
Terminology Conventions..............................................................................................xxxv
Part I
e500 Core
1.1
1.1.1
1.1.2
1.2
1.3
1.3.1
1.4
1.5
1.5.1
1.5.2
1.5.3
1.6
1.7
1.8
1.8.1
1.8.2
1.8.3
1.8.4
1.8.5
1.9
1.9.1
1.9.2
Chapter 1
www.DataSheet4U.comCore Complex Overview
Overview.......................................................................................................................... 1-1
Upward Compatibility ................................................................................................. 1-3
Core Complex Summary ............................................................................................. 1-3
e500 Processor and System Version Numbers................................................................. 1-5
Features ............................................................................................................................ 1-5
e500v2 Differences .................................................................................................... 1-11
Instruction Set ................................................................................................................ 1-12
Instruction Flow............................................................................................................. 1-14
Initial Instruction Fetch.............................................................................................. 1-14
Branch Detection and Prediction ............................................................................... 1-14
e500 Execution Pipeline ............................................................................................ 1-16
Programming Model ...................................................................................................... 1-18
On-Chip Cache Implementation .................................................................................... 1-20
Interrupts and Exception Handling ................................................................................ 1-20
Exception Handling ................................................................................................... 1-20
Interrupt Classes ........................................................................................................ 1-21
Interrupt Types ........................................................................................................... 1-21
Upper Bound on Interrupt Latencies ......................................................................... 1-22
Interrupt Registers...................................................................................................... 1-22
Memory Management.................................................................................................... 1-24
Address Translation ................................................................................................... 1-26
MMU Assist Registers (MAS0–MAS4 and MAS6–MAS7)..................................... 1-27
Freescale Semiconductor
PowerPC e500 Core Family Reference Manual, Rev. 1
v
www.DataSheet4U.com
5 Page www.DataSheet4U.com
Paragraph
Number
Contents
Title
Page
Number
Chapter 4
Execution Timing
4.1
4.2
4.3
4.3.1
4.3.2
4.3.2.1
4.3.2.2
4.3.2.3
4.3.3
4.3.3.1
4.3.3.2
4.3.3.3
4.3.4
4.3.5
4.3.5.1
4.3.5.2
4.4
4.4.1
4.4.1.1
4.4.1.2
4.4.1.3
4.4.1.3.1
4.4.1.3.2
4.4.1.3.3
4.4.1.3.4
4.4.2
4.4.2.1
4.4.3
4.4.3.1
4.4.3.2
4.4.4
4.4.4.1
4.5
4.6
Terminology and Conventions......................................................................................... 4-1
Instruction Timing Overview........................................................................................... 4-4
General Timing Considerations ..................................................................................... 4-10
General Instruction Flow ........................................................................................... 4-11
Instruction Fetch Timing Considerations................................................................... 4-12
L1 and L2 TLB Access Times ............................................................................... 4-12
Interrupts Associated with Instruction Fetching.................................................... 4-12
Cache-Related Latency.......................................................................................... 4-13
Dispatch, Issue, and Completion Considerations ...................................................... 4-14
GPR and CR Rename Register Operation ............................................................. 4-15
LR and CTR Shadow (Speculative) Registers....................................................... 4-15
Instruction Serialization......................................................................................... 4-15
Interrupt Latency........................................................................................................ 4-16
Memory Synchronization Timing Considerations..................................................... 4-17
msync Instruction Timing Considerations ............................................................ 4-17
www.DataSheet4U.commbar Instruction Timing Considerations.............................................................. 4-17
Execution ....................................................................................................................... 4-18
Branch Unit Execution............................................................................................... 4-18
Branch Instructions and Completion ..................................................................... 4-18
BTB Branch Prediction and Resolution ................................................................ 4-20
BTB Operations ..................................................................................................... 4-21
BTB Locking ..................................................................................................... 4-23
BTB Locking APU Programming Model.......................................................... 4-24
BTB Operations Controlled by BUCSR............................................................ 4-24
BTB Special Cases—Phantom Branches and Multiple Matches ...................... 4-25
Load/Store Unit Execution ........................................................................................ 4-25
Load/Store Unit Queueing Structures.................................................................... 4-25
Simple and Multiple Unit Execution ......................................................................... 4-27
MU Divide Execution............................................................................................ 4-28
MU Floating-Point Execution................................................................................ 4-29
Load/Store Execution ................................................................................................ 4-29
Effect of Operand Placement on Performance ...................................................... 4-30
Memory Performance Considerations ........................................................................... 4-30
Instruction Latency Summary........................................................................................ 4-31
Freescale Semiconductor
PowerPC e500 Core Family Reference Manual, Rev. 1
xi
www.DataSheet4U.com
11 Page |
Páginas | Total 30 Páginas | |
PDF Descargar | [ Datasheet E500CORERM.PDF ] |
Número de pieza | Descripción | Fabricantes |
E500CORERM | PowerPC e500 Core Family | Freescale |
Número de pieza | Descripción | Fabricantes |
SLA6805M | High Voltage 3 phase Motor Driver IC. |
Sanken |
SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |