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PDF M6MGB321S8TP Data sheet ( Hoja de datos )
| Número de pieza | M6MGB321S8TP | |
| Descripción | CMOS SRAM | |
| Fabricantes | Renesas | |
| Logotipo |  |
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Renesas LSIs
M6MGB/T321S8TP
33,554,432-BIT (2,097,152 - WORD BY 16-BIT/4,194,304-WORD BY 8-BIT) CMOS
3.0V-ONLY FLASH MEMORY &
8,388,608-BIT (524,288-WORD BY 16-BIT/1,048,576-WORD BY 8-BIT) CMOS SRAM
Stacked - µ MCP (micro Multi Chip Package)
Description
The M6MGB/T321S8TP is a Stacked micro Multi Chip
M6MGB/T321S8TP provides for Software Lock Release
Package (S- µMCP) that contents 32M-bit Flash memory and function. Usually, all memory blocks are locked and can not
8M-bit Static RAM in a 52-pin TSOP.
be programed or erased, when F-WP# is low. Using
32M-bit Flash memory is a 4,194,304 bytes / 2,097,152 words,
3.0V-only, and high performance non-volatile memory
Software Lock Release function, program or erase operation
can be excuted.
fabricated by CMOS technology for the peripheral circuit and Features
DINOR (Divided bit-line NOR) architecture for the memory cell. Access Time
Flash
85ns (Max.)
8M-bit SRAM is a 1,048,576 bytes / 524,288 words
asynchronous SRAM fabricated by silicon-gate CMOS
SRAM
85ns (Max.)
technology.
Supply Voltage
VCC=2.7 ~ 3.0V
M6MGB/T321S8TP is suitable for the application of the
mobile-communication-system to reduce both the mount
space and weight.
Ambient Temperature
Package
Application
Mobile communication products
Ta=-20 ~ 85 °C
52pin TSOP(Type-II),
Lead pitch 0.4mm
PIN CONFIGURATION (TOP VIEW)
A15 1
52 A16
A14 2
51 BYTE#
A13
A12
A11
A10
A9
3
4
5
6
7
www.DataSheet4U.comA8 8
50 S-UB#
49 GND
48 S-LB#
47 DQ15/A-1
46 DQ7
45 DQ14
A19 9
44 DQ6
S-CE1#
10
43 DQ13
WE#
11
42 DQ5
F-RP#
12
41 DQ12
F-WP#
S-VCC
13
14
M6MGB/T321S8TP
40
39
DQ4
F-VCC
S-CE2
15
38 DQ11
F-RY/BY#
16
37 DQ3
A20 17
36 DQ10
A18 18
35 DQ2
A17 19
34 DQ9
A7 20
33 DQ1
A6 21
32 DQ8
A5 22
31 DQ0
A4 23
30 OE#
A3 24
29 GND
A2 25
28 F-CE#
A1 26
27 A0
10.49 mm
F-VCC
S-VCC
GND
A-1-A18
A19-A20
DQ0-DQ15
F-CE#
S-CE#,S-CE2
OE#
WE#
F-WP#
F-RP#
F-RY/BY#
BYTE#
S-LB#
S-UB#
:Vcc for Flash
:Vcc for SRAM
:GND for Flash/SRAM
:Flash/SRAM common Address
:Address for Flash
:Data I/O
:Flash Chip Enable
:SRAM Chip Enable
:Flash/SRAM Output Enable
:Flash/SRAM Write Enable
:Flash Write Protect
:Flash Reset Power Down
:Flash Ready/Busy
:Flash/SRAM Byte Enable
:SRAM Lower Byte
:SRAM Upper Byte
Outline 52PTG-A
1 Rev.3.0_48a_abbz
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