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PDF LRS1383H Data sheet ( Hoja de datos )
| Número de pieza | LRS1383H | |
| Descripción | 32M ( X16) Boot Block Flash & 8M ( X16) SRAM | |
| Fabricantes | Sharp Microelectronics | |
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PRELIMINARY PRODUCT SPECIFICATIONS
®
Integrated Circuits Group
LRS1383H
32M (x16)wBwoowtS.BDtlaoacctkakSFelhadseheCatn4hdUip8.cMo(mx16) SRAM
(Model No.: LRS1383H)
Spec No.: MFM2-J14418
Issue Date: April 24, 2002
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LRS1383H
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1. Description
The LRS1383H is a combination memory organized as 2,097,152 x16 bit flash memory and 524,288 x16 bit static RAM in one
package.
Features
- Power supply
• • • • 2.7V to 3.3V
- Operating temperature
• • • • -25°C to +85°C
- Not designed or rated as radiation hardened
- 72pin CSP (LCSP072-P-0811) plastic package
- Flash memory has P-type bulk silicon, and SRAM has P-type bulk silicon
Flash Memory
- Access Time
• • • • 70 ns (Max.)
- Power supply current (The current for F-VCC pin and F-VPP pin)
Read
••••
Word write
••••
25 mA (Max. tCYCLE = 200ns, CMOS Input)
60 mA (Max.)
Block erase
• • • • 30 mA (Max.)
Reset Power-Down
• • • • 25 µA (Max. F-RST = GND ± 0.2V,
Standby
••••
25 µA
IOUT (F-RY/BY) = 0mA)
(Max. F-CE = F-RST = F-VCC ± 0.2V)
- Optimized Array Blocking Architecture
Eight 4K-word Parameter Blocks
www.DataSheet4U.comSixty-Three 32K-word Main Blocks
Bottom Parameter Location
- Extended Cycling Capability
100,000 Block Erase Cycles
(F-VPP = 1.65V to 3.3V)
1,000 Block Erase Cycles and total 80 hours (F-VPP = 11.7V to 12.3V)
- Enhanced Automated Suspend Options
Word Write Suspend to Read
Block Erase Suspend to Word Write
Block Erase Suspend to Read
- OTP Block
4 Word + 4 Word Array
SRAM
- Access Time
- Power Supply current
Operating current
Standby current
Data retention current
• • • • 70 ns (Max.)
••••
••••
••••
••••
50 mA
8 mA
25 µA
25 µA
(Max. tRC, tWC = Min.)
(Max. tRC, tWC = 1µs, CMOS Input)
(Max.)
(Max. S-VCC = 3.0V)
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LRS1383H
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5. Command Definitions for Flash Memory(11)
5.1 Command Definitions
Command
Bus
Cycles
Req’d
Notes
First Bus Cycle
Oper(1) Address(2) Data(3)
Second Bus Cycle
Oper(1) Address(2) Data(3)
Read Array
1 2 Write PA FFH
Read Identifier Codes/OTP
≥ 2 2,3,4 Write
PA
90H Read IA or OA ID or OD
Read Query
≥ 2 2,3,4 Write
PA
98H Read
QA
QD
Read Status Register
2
2,3 Write
PA
70H Read
PA
SRD
Clear Status Register
1
2
Write
PA
50H
Block Erase
2
2,3,5 Write
BA
20H Write
BA
D0H
Full Chip Erase
2 2,5,9 Write X
30H Write
X
D0H
Program
2
2,3,5,6 Write
WA
40H or
10H
Write
WA
WD
Page Buffer Program
≥ 4 2,3,5,7 Write
WA
E8H Write
WA
N-1
Block Erase and (Page Buffer)
Program Suspend
1
2,8,9 Write
PA
B0H
Block Erase and (Page Buffer)
Program Resume
1
2,8,9 Write
PA
D0H
Set Block Lock Bit
2
2
Write
BA
60H Write
BA
Clear Block Lock Bit
www.DataSheet4U.comSet Block Lock-down Bit
2
2,10 Write
BA
60H Write
BA
2
2
Write
BA
60H Write
BA
01H
D0H
2FH
OTP Program
2 2,3,9 Write OA C0H Write OA
OD
Set Partition Configuration
Register
2 2,3 Write PCRC 60H Write PCRC 04H
Notes:
1. Bus operations are defined in 3.1 Bus Operation.
2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus
cycle.
X=Any valid address within the device.
PA=Address within the selected partition.
IA=Identifier codes address (See 5.2 Identifier Codes and OTP Address for Read Operation).
QA=Query codes address. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit.
WA=Address of memory location for the Program command or the first address for the Page Buffer Program command.
OA=Address of OTP block to be read or programmed (See 5.3 OTP Block Address Map).
PCRC=Partition configuration register code presented on the address A0-A15.
3. ID=Data read from identifier codes (See 5.2 Identifier Codes and OTP Address for Read Operation).
QD=Data read from query database. Refer to the LH28F320BF, LH28F640BF, LH28F128BF series Appendix for details.
SRD=Data read from status register. See 6. Status Register Definition for a description of the status register bits.
WD=Data to be programmed at location WA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
OD=Data to be programmed at location OA. Data is latched on the rising edge of F-WE or F-CE (whichever goes high first).
N-1=N is the number of the words to be loaded into a page buffer.
4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock
configuration code, partition configuration register code and the data within OTP block (See 5.2 Identifier Codes and OTP
Address for Read Operation).
The Read Query command is available for reading CFI (Common Flash Interface) information.
5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked
block can be erased or programmed when F-RST is VIH.
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