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W78E62B 데이터시트 PDF




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부품번호 W78E62B 기능
기능 8-Bit Microcontroller
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W78E62B 데이터시트, 핀배열, 회로
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W78E62B
8-BIT MICROCONTROLLER
GENERAL DESCRIPTION
The W78E62B is an 8-bit microcontroller which has an in-system programmable MTP-ROM for
firmware updating. The instruction set of the W78E62B is fully compatible with the standard 8052.
The W78E62B contains a 64K bytes of main MTP-ROM and a 4K bytes of auxiliary MTP-ROM which
allows the contents of the 64KB main MTP-ROM to be updated by the loader program located at the
4KB auxiliary MTP-ROM; 512 bytes of on-chip RAM; four 8-bit bi-directional and bit-addressable I/O
ports; an additional 4-bit port P4; three 16-bit timer/counters; a serial port. These peripherals are
supported by a eight sources two-level interrupt capability. To facilitate programming and verification,
the MTP-ROM inside the W78E62B allows the program memory to be programmed and read
electronically. Once the code is confirmed, the user can protect the code for security.
The W78E62B microcontroller has two power reduction modes, idle mode and power-down mode,
both of which are software selectable. The idle mode turns off the processor clock but allows for
continued peripheral operation. The power-down mode stops the crystal oscillator for minimum power
consumption. The external clock can be stopped at any time and in any state without affecting the
processor.
FEATURES
Fully static design 8-bit CMOS microcontroller up to 40 MHz.
www.DataSheet4U.com64K bytes of in-system programmable MTP-ROM for Application Program (APROM).
4K bytes of auxiliary MTP-ROM for Loader Program (LDROM).
Low standby current at full supply voltage.
512 bytes of on-chip RAM. (including 256 bytes of AUX-RAM, software selectable)
64K bytes program memory address space and 64K bytes data memory address space.
Four 8-bit bi-directional ports.
One 4-bit multipurpose programmable port.
Build-in 74373 and 74244 logical functions on Port 2.(software programmable)
Three 16-bit timer/counters
One full duplex serial port
Eight-sources, two-level interrupt capability
Built-in power management
Code protection
PACKAGE
PLCC 44: W78E62BP-40
LQFP 48: W78E62BD-40
Publication Release Date: June 1999
- 1 - Revision A1
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W78E62B pdf, 반도체, 판매, 대치품
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W78E62B
In mode 2 , P4.0P4.3 are write data strobe signals which are synchronized with WR signal at
specified addresses. These signals can be used as chip-select signals for external peripherals.
In mode 3, P4.0P4.3 are read data strobe signals which are synchronized with RD or WR signal at
specified addresses. These signals can be used as chip-select signals for external peripherals.
When Port 4 is configured with the feature of chip-select signals, the chip-select signal address range
depends on the contents of the SFR P4xAH, P4xAL, P4CONA and P4CONB. The registers P4xAH
and P4xAL contain the 16-bit base address of P4.x. The registers P4CONA and P4CONB contain the
control bits to configure the Port 4 operation mode.
BLOCK DIAGRAM
P1.0
P1.7
P3.0
P3.7
P4.0
P4.3
Port Port 1
1
Latch
ACC
B
Interrupt
T1 T2
Port 0
Latch
Port
0
Timer
2
DPTR
Timer
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Timer
1
PSW
Stack
ALU Pointer
Temp Reg.
PC
UART
Incrementor
Addr. Reg.
Port Port 3
3
Latch
INT2 / INT3
Port 4
Port Latch
4
Instruction
Decoder
&
Sequencer
Bus & Clock
Controller
SFR RAM
Address
512 bytes
RAM & SFR
64KB
MTP-ROM
4KB
MTP-ROM
Port 2
Latch
Port
2
Oscillator
Reset Block
Power control
XTAL1 XTAL2
ALE
PSEN
RST
VCC
Vss
P0.0
P0.7
P2.0
P2.7
-4-
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W78E62B 전자부품, 판매, 대치품
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W78E62B
Power Management
Idle Mode
The idle mode is entered by setting the IDL bit in the PCON register. In the idle mode, the internal
clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The
processor will exit idle mode when either an interrupt or a reset occurs.
Power-down Mode
When the PD bit in the PCON register is set, the processor enters the power-down mode. In this
mode all of the clocks are stopped, including the oscillator. To exit from power-down mode is by a
hardware reset or external interrupts INT0 to INT3 when enabled and set to level triggered.
Reduce EMI Emission
The W78E62B allows user to diminish the gain of on-chip oscillator amplifier by using programmer to
clear the B7 bit of security register. Once B7 is set to 0, a half of gain will be decreased. Care must
be taken if user attempts to diminish the gain of oscillator amplifier, reducing a half of gain may affect
the external crystal operating improperly at high frequency above 24 MHz. The value of R and C1,C2
may need some adjustment while running at lower gain.
Reset
The external RESET signal is sampled at S5P2. To take effect, it must be held high for at least two
www.DataSheet4U.commachine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to
deglitch the reset line when the W78E62B is used with an external RC network. The reset logic also
has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are
initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the
other SFR registers except SBUF to 00H. SBUF is not reset.
W78E62B Special Function Registers (SFRs) and Reset Values
F8
F0 +B
00000000
E8
CHPENR
00000000
E0 +ACC
00000000
D8 +P4
xxxx1111
D0 +PSW
00000000
C8 +T2CON
00000000
C0 XICON
00000000
B8 +IP
00000000
RCAP2L
00000000
P4CONA
00000000
RCAP2H
00000000
P4CONB
00000000
TL2
00000000
SFRAL
00000000
TH2
00000000
SFRAH
00000000
SFRFD
00000000
FF
F7
EF
E7
DF
D7
CF
SFRCN
00000000
CHPCON
0xx00000
C7
BF
Publication Release Date: June 1999
- 7 - Revision A1
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W78E62B

8-Bit Microcontroller

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