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PDF AD9889 Data sheet ( Hoja de datos )
| Número de pieza | AD9889 | |
| Descripción | High Performance HDMI/DVI Transmitter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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High Performance
HDMI™/DVI Transmitter
AD9889
FEATURES
FUNCTIONAL BLOCK DIAGRAM
HDMI/DVI transmitter compatible with HDMI 1.1 and
HDCP 1.1
Single 1.8 V power supply
Video/audio inputs are 3.3 V tolerant
80-lead, Pb-free LQFP
Digital video
80 MHz operation supports all video formats from 480i to
1080i and 720p
Programmable 2-way color space converter
Supports RGB, YCbCr, DDR, ITU656 formats
Auto input video format detection
Digital audio
Supports standard S/PDIF for stereo or compressed audio
up to 192 kHz
8-channel LPCM I2S audio up to 192 kHz
HTPG
SCL SDA MCL MDA
REGISTER
CONFIGURATION
LOGIC
I2C
SLAVE
I2C
MASTER
HDCP
CONTROLLER
DDSDA
DDCSCL
CLK
VSYNC
HSYNC
DE
D[23:0]
VIDEO
DATA
CAPTURE
HDCP
CIPHER
COLOR
SPACE
CONVERSION
4:2:2
TO
4:4:4
CONVERSION
XOR
MASK
HDM
ITX
CORE
SWING_ADJ
Tx0[1:0]
Tx1[1:0]
Tx2[1:0]
TxC[1:0]
Special features for easy system design
On-chip MPU to perform HDCP operations
On-chip I2C master to handle EDID reading
5 V tolerant I2C and MPD I/Os, no extra device needed
S/PDIF
MCLK
I2S[3:0]
AUDIO
DATA
CAPTURE
Figure 1.
No audio master clock needed for S/PDIF support
www.DataSheet4U.comAPPLICATIONS
AD9889
05675-001
DVD players and recorders
Digital set-top boxes
AV receivers
Digital cameras and camcorders
GENERAL DESCRIPTION
The AD9889 is an 80 MHz, high-definition multimedia inter-
face (HDMITM 1.1) transmitter. It supports HDTV formats up
to 1080i and 720p, and graphic resolutions up to XGA (1024 ×
768 @ 75 Hz). With the inclusion of HDCP, the AD9889 allows
the secure transmission of protected content as specified by the
HDCP 1.1 protocol.
The AD9889 supports both S/PDIF and 8-channel I2S audio.
Its high fidelity 8-channel I2S can transmit either stereo or
7.1 surround audio at 192 kHz. The S/PDIF can carry stereo
LPCM (linear pulse code modulation) audio or compressed
audio including Dolby® Digital, DTS®, and THX®.
The AD9889 helps to reduce system design complexity and cost
by incorporating such features as HDCP master, I2C master for
EDID reading, a single 1.8 V power supply, and 5 V tolerance
on I2C and hot plug detect pins.
Fabricated in an advanced CMOS process, the AD9889 is pro-
vided in a space-saving, 80-lead, surface-mount, Pb-free plastic
LQFP and is specified over the 0°C to 70°C temperature range.
EVALUATION KITS AND OTHER RESOURCES
Evaluation kits, reference design schematics, software quick
start guide, and codes are available from Analog Devices local
sales and marketing personnel.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
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One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2005 Analog Devices, Inc. All rights reserved.
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AD9889
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Digital Inputs
Digital Output Current
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Maximum Case Temperature
Rating
5 V to 0.0 V
20 mA
−40°C to +85°C
−65°C to +150°C
150°C
150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
EXPLANATION OF TEST LEVELS
Table 3.
Level Test
I 100% production tested.
II 100% production tested at 25°C and sample tested at
specified temperatures.
III Sample tested only.
IV Parameter is guaranteed by design and characterization
testing.
V Parameter is a typical value only.
VI 100% production tested at 25°C; guaranteed by design
and characterization testing.
VII Limits defined by HDMI specification.
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ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
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AD9889
YCbCr 4:2:2 Formats (24 Bits, 20 Bits, or 16 Bits) with Embedded Syncs, Input ID = 2
An input with YCbCr 4:2:2 with embedded syncs can be selected by setting the input ID (R0x15[3:1]) to 0b010. HS YNC and VSYNC are
embedded as Start of Active Video (SAV) and End of Active Video (EAV). The input CS (R0x16[0]) must be set to 0b1 for proper
operation. The data bit width (24 = 12 bits, 20 = 10 bits, or 16 = 8 bits) must be set with R0x16[5:4]. The three input pin assignment styles
are shown in Table 12. The input style can be set in R0x16[3:2]. The only difference between Input ID 1 and Input ID 2 is that the syncs
on ID 2 are embedded in the data much like ITU 656 running at 1× clock and double width.
Table 12.
Data <23:0>
Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
YCbCr 4:2:2 Sep. Cb[11:4]
Y[11:4]
Cb[3:0]
Y[3:0]
Sync (24 bit)
Cr[11:4]
Y[11:4]
Cr[3:0]
Y[3:0]
YCbCr 4:2:2 Sep. Cb[9:2]
Y[9:2]
Cb[1:0]
Y[1:0]
Sync (20 bit)
Cr[9:2]
Y[9:2]
Cr[1:0]
Y[1:0]
YCbCr 4:2:2 Sep. Cb[7:0]
Y[7:0]
Sync (16 bit)
Cr[7:0]
Y[7:0]
Style 2
24-bit
Cb[11:0]
Y[11:0]
Cr[11:0]
Y[11:0]
20-bit
Cb[9:0]
Y[9:0]
Cr[9:0]
Y[9:0]
16-bit
Cb[7:0]
Y[7:0]
Cr[7:0]
Y[7:0]
www.DataSheet4U.com24-bit
Y[11:0]
Style 3
Cb[11:0]
Y[11:0]
Cr[11:0]
20-bit
Y[9:0]
Cb[9:0]
Y[9:0]
Cr[9:0]
16-bit
Y[7:0]
Cb[7:0]
Y[7:0]
Cr[7:0]
YCbCr 4:2:2 Formats (Double Data Rate) Formats (12, 10, or 8 bits) with Separate Syncs, Input ID = 3
An input with YCbCr 4:2:2 DDR data and separate syncs can be selected by setting the input ID (R0x15[3:1]) to 0b011. The input CS
(R0x16 [0]) must be set to 0b1. The data bit width (12 bits, 10 bits, or 8 bits) must be set with R0x16[5:4]. The two input pin assignment
styles are shown in Table 13. The input style can be set in R0x16[3:2].
Table 13.
Data <23:0>
Input Format 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Style 1
12-bit
Cb/Y/Cr/Y[11:4]
[3:0]
10-bit
Cb/Y/Cr/Y[9:2]
[1:0]
8-bit Cb/Y/Cr/Y[7:0]
Style 2
12-bit
Cb/Y/Cr/Y[11:0]
10-bit
Cb/Y/Cr/Y[9:0]
8-bit Cb/Y/Cr/Y[7:0]
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