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부품번호 | GE28F640J3 기능 |
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기능 | Intel StrataFlash Memory (J3) | ||
제조업체 | Intel Corporation | ||
로고 | |||
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Intel StrataFlash® Memory (J3)
256-Mbit (x8/x16)
Product Features
Datasheet
■ Performance
■ Architecture
— 110/115/120/150 ns Initial Access Speed — Multi-Level Cell Technology: High
— 125 ns Initial Access Speed (256 Mbit
density only)
— 25 ns Asynchronous Page mode Reads
— 30 ns Asynchronous Page mode Reads
(256Mbit density only)
— 32-Byte Write Buffer
—6.8 µs per byte effective
programming time
■ Software
Density at Low Cost
— High-Density Symmetrical 128-Kbyte
Blocks
—256 Mbit (256 Blocks) (0.18µm only)
—128 Mbit (128 Blocks)
—64 Mbit (64 Blocks)
—32 Mbit (32 Blocks)
■ Quality and Reliability
— Operating Temperature:
-40 °C to +85 °C
— Program and Erase suspend support
— 100K Minimum Erase Cycles per Block
— Flash Data Integrator (FDI), Common
— 0.18 µm ETOX™ VII Process (J3C)
Flash Interface (CFI) Compatible
■ Security
— 0.25 µm ETOX™ VI Process (J3A)
■ Packaging and Voltage
— 128-bit Protection Register
— 56-Lead TSOP Package
www.DataSheet4U.com—64-bit Unique Device Identifier
—64-bit User Programmable OTP Cells
— 64-Ball Intel® Easy BGA Package
— Lead-free packages available
— Absolute Protection with VPEN = GND
— Individual Block Locking
— 48-Ball Intel® VF BGA Package (32 and
64 Mbit) (x16 only)
— Block Erase/Program Lockout during
Power Transitions
— VCC = 2.7 V to 3.6 V
— VCCQ = 2.7 V to 3.6 V
Capitalizing on Intel’s 0.25 and 0.18 micron, two-bit-per-cell technology, the Intel StrataFlash® Memory (J3)
device provides 2X the bits in 1X the space, with new features for mainstream performance. Offered in 256-
Mbit (32-Mbyte), 128-Mbit (16-Mbyte), 64-Mbit, and 32-Mbit densities, the J3 device brings reliable, two-bit-
per-cell storage technology to the flash market segment. Benefits include more density in less space, high-speed
interface, lowest cost-per-bit NOR device, support for code and data storage, and easy migration to future
devices.
Using the same NOR-based ETOX™ technology as Intel’s one-bit-per-cell products, the J3 device takes
advantage of over one billion units of flash manufacturing experience since 1987. As a result, J3 components
are ideal for code and data applications where high density and low cost are required. Examples include
networking, telecommunications, digital set top boxes, audio recording, and digital imaging.
By applying FlashFile™ memory family pinouts, J3 memory components allow easy design migrations from
existing Word-Wide FlashFile memory (28F160S3 and 28F320S3), and first generation Intel StrataFlash®
memory (28F640J5 and 28F320J5) devices.
J3 memory components deliver a new generation of forward-compatible software support. By using the
Common Flash Interface (CFI) and the Scalable Command Set (SCS), customers can take advantage of density
upgrades and optimized write capabilities of future Intel StrataFlash® memory devices. Manufactured on Intel®
0.18 micron ETOX™ VII (J3C) and 0.25 micron ETOX™ VI (J3A) process technology, the J3 memory device
provides the highest levels of quality and reliability.
Notice: This document contains information on new products in production. The specifications are
subject to change without notice. Verify with your local Intel sales office that you have the latest
datasheet before finalizing a design.
Order Number: 290667-021
March 2005
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Contents
9.2 Device Commands ............................................................................................................. 35
10.0 Read Operations.......................................................................................................................... 37
10.1
10.2
10.3
Read Array.......................................................................................................................... 37
10.1.1 Asynchronous Page Mode Read ........................................................................... 37
10.1.2 Enhanced Configuration Register (ECR)............................................................... 38
Read Identifier Codes ......................................................................................................... 39
10.2.1 Read Status Register............................................................................................. 39
Read Query/CFI.................................................................................................................. 41
11.0 Programming Operations ........................................................................................................... 42
11.1
11.2
11.3
11.4
Byte/Word Program ............................................................................................................ 42
Write to Buffer..................................................................................................................... 42
Program Suspend............................................................................................................... 43
Program Resume................................................................................................................ 43
12.0 Erase Operations......................................................................................................................... 44
12.1 Block Erase......................................................................................................................... 44
12.2 Block Erase Suspend ......................................................................................................... 44
12.3 Erase Resume .................................................................................................................... 45
13.0 Security Modes ............................................................................................................................ 46
13.1 Set Block Lock-Bit............................................................................................................... 46
13.2 Clear Block Lock-Bits.......................................................................................................... 46
13.3 Protection Register Program .............................................................................................. 47
www.DataSheet4U.com13.3.1 Reading the Protection Register............................................................................ 47
13.3.2 Programming the Protection Register.................................................................... 47
13.3.3 Locking the Protection Register............................................................................. 47
13.4 Array Protection .................................................................................................................. 49
14.0 Special Modes.............................................................................................................................. 50
14.1 Set Read Configuration Register Command ...................................................................... 50
14.2 Status (STS) ....................................................................................................................... 50
Appendix A Common Flash Interface.................................................................................................52
Appendix B Flow Charts ......................................................................................................................59
Appendix C Design Considerations ...................................................................................................68
Appendix D Additional Information ....................................................................................................70
Appendix E Ordering Information.......................................................................................................71
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1.0
1.1
1.2
256-Mbit J3 (x8/x16)
Introduction
This document describes the Intel StrataFlash® Memory (J3) device. It includes a description of
device features, operations, and specifications.
Nomenclature
AMIN: AMIN = A0 for x8
AMIN = A1 for x16
AMAX: 32 Mbit AMAX = A21
64 Mbit AMAX = A22
128 Mbit AMAX = A23
256 Mbit AMAX = A24
Block: A group of flash cells that share common erase circuitry and erase simultaneously
Clear:
Indicates a logic zero (0)
CUI:
Command User Interface
MLC:
Multi-Level Cell
OTP:
One Time Programmable
PLR:
Protection Lock Register
PR: Protection Register
PRD
Protection Register Data
Program: To write data to the flash array
RFU:
Reserved for Future Use
Set: Indicates a logic one (1)
www.DataSheet4U.comSR: Status Register
SRD:
Status Register Data
VPEN: Refers to a signal or package connection name
VPEN:
WSM:
Refers to timing or voltage levels
Write State Machine
ECR:
Extended Configuration Register
XSR:
eXtended Status Register
Conventions
0x:
0b:
k (noun):
M (noun):
Nibble
Byte:
Word:
Kword:
Kb:
KB:
Mb:
MB:
Brackets:
Hexadecimal prefix
Binary prefix
1,000
1,000,000
4 bits
8 bits
16 bits
1,024 words
1,024 bits
1,024 bytes
1,048,576 bits
1,048,576 bytes
Square brackets ([]) will be used to designate group membership or to define a
group of signals with similar function (i.e., A[21:1], SR[4,1] and D[15:0]).
Datasheet
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DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |