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기능 Wireless Memory
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GE28F640L30 데이터시트, 핀배열, 회로
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1.8 Volt Intel StrataFlash® Wireless
Memory with 3.0-Volt I/O (L30)
28F640L30, 28F128L30, 28F256L30
Datasheet
Product Features
High performance Read-While-Write/Erase
Software
— 90 ns initial access
— 20 µs (Typ) program suspend
— 50MHz with zero wait state, 17 ns clock-to-data
— 20 µs (Typ) erase suspend
output synchronous-burst mode
— Intel® Flash Data Integrator (FDI) optimized
— 25 ns asynchronous-page mode
— Basic Command Set (BCS) and Extended
— 4-, 8-, 16-, and continuous-word burst mode
Command Set (ECS) compatible
— Burst suspend
— Common Flash Interface (CFI) capable
— Programmable WAIT configuration
Security
— Buffered Enhanced Factory Programming
(Buffered EFP): 3.5 µs/byte (Typ)
— OTP space:
— 1.8 V low-power buffered and non-buffered
— 64 unique device identifier bits
programming @ 10 µs/byte (Typ)
— 64 user-programmable OTP bits
Architecture
— Asymmetrically-blocked architecture
— Multiple 8-Mbit partitions: 64Mb and 128Mb
devices
— Additional 2048 user-programmable OTP
bits
— Absolute write protection: VPP = GND
— Multiple 16-Mbit partitions: 256Mb devices
— Power-transition erase/program lockout
www.DataSheet4U.com— Four 16-KWord parameter blocks: top or
bottom configurations
— 64K-Word main blocks
— Individual zero-latency block locking
— Individual block lock-down
Quality and Reliability
— Dual-operation: Read-While-Write (RWW) or
Read-While-Erase (RWE)
— Expanded temperature: –25° C to +85° C
— Minimum 100,000 erase cycles per block
— Status register for partition and device status
— ETOX™ VIII process technology (0.13 µm)
Power
Density and Packaging
— 1.7 V - 2.0 V VCC operation
— I/O voltage: 2.2 V - 3.3 V
— 64-, 128- and 256-Mbit density in VF BGA
packages
— Standby current: 30 µA (Typ)
— 16-bit wide data bus
— 4-Word synchronous read current: 17 mA (Typ)
@ 54 MHz
— Automatic Power Savings (APS) mode
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O product is the latest generation of
Intel StrataFlash® memory devices featuring flexible, multiple-partition, dual operation. It provides high
performance synchronous-burst read mode and asynchronous read mode using 1.8 volt low-voltage, multi-
level cell (MLC) technology.
The multiple-partition architecture enables background programming or erasing to occur in one partition
while code execution or data reads take place in another partition. This dual-operation architecture also
allows two processors to interleave code operations while program and erase operations take place in the
background.
The 1.8 Volt Intel StrataFlash® wireless memory with 3-Volt I/O device is manufactured using Intel
0.13 µm ETOX™ VIII process technology. It is available in industry-standard chip scale packaging.
.
Notice: This document contains information on products in the design phase of
development. The information here is subject to change without notice. Do not finalize
a design with this information.
Order Number: 251903-002
February 2003
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GE28F640L30 pdf, 반도체, 판매, 대치품
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28F640L30, 28F128L30, 28F256L30
6.0
7.0
8.0
9.0
10.0
11.0
5.5 Program Resume ................................................................................................ 32
5.6 Program Protection ............................................................................................. 32
Erase Operations ..................................................................................................... 33
6.1 Block Erase ......................................................................................................... 33
6.2 Erase Suspend.................................................................................................... 33
6.3 Erase Resume .................................................................................................... 34
6.4 Erase Protection.................................................................................................. 34
Security Modes ......................................................................................................... 35
7.1 Block Locking ...................................................................................................... 35
7.1.1 Lock Block .............................................................................................. 35
7.1.2 Unlock Block .......................................................................................... 35
7.1.3 Lock-Down Block ................................................................................... 35
7.1.4 Block Lock Status................................................................................... 36
7.1.5 Block Locking During Suspend .............................................................. 36
7.2 Protection Registers ............................................................................................ 37
7.2.1 Reading the Protection Registers .......................................................... 38
7.2.2 Programming the Protection Registers .................................................. 39
7.2.3 Locking the Protection Registers ........................................................... 39
Dual-Operation Considerations ......................................................................... 40
8.1 Memory Partitioning ............................................................................................ 40
8.2 Read-While-Write Command Sequences ........................................................... 40
www.DataSheet4U.com8.2.1 Simultaneous Operation Details............................................................. 41
8.2.2 Synchronous and Asynchronous Read-While-Write Characteristics
and Waveforms ...................................................................................... 41
8.2.2.1 Write operation to asynchronous read transition....................... 41
8.2.2.2 Synchronous read to write operation transition ......................... 42
8.2.3 Read Operation During Buffered Programming Flowchart..................... 42
8.3 Simultaneous Operation Restrictions .................................................................. 43
Special Read States ................................................................................................ 44
9.1 Read Status Register .......................................................................................... 44
9.1.1 Clear Status Register ............................................................................. 45
9.2 Read Device Identifier ......................................................................................... 45
9.3 CFI Query............................................................................................................ 46
Power and Reset ...................................................................................................... 47
10.1
10.2
10.3
10.4
Power-Up/Down Characteristics ......................................................................... 47
Power Supply Decoupling ................................................................................... 47
Automatic Power Saving (APS) .......................................................................... 47
Reset Characteristics .......................................................................................... 47
Thermal and DC Characteristics........................................................................ 49
11.1
11.2
11.3
11.4
Absolute Maximum Ratings ................................................................................ 49
Operating Conditions .......................................................................................... 49
DC Current Characteristics ................................................................................. 50
DC Voltage Characteristics ................................................................................. 51
4
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GE28F640L30 전자부품, 판매, 대치품
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1.0
1.1
1.2
28F640L30, 28F128L30, 28F256L30
Introduction
This document provides information about the 1.8 Volt Intel StrataFlash® wireless memory with
3-Volt I/O (L30) device. This document describes the L30 flash memory device features, operation,
and specifications.
Nomenclature
1.8 V: VCC voltage range of 1.7 V – 2.0 V (except where noted)
3.0 V Range: VCCQ voltage range of 2.2 V – 3.3 V
VPP = 9.0 V: VPP voltage range of 8.5 V – 9.5 V
Block: A group of bits, bytes or words within the flash memory array that erase simultaneously
when the Erase command is issued to the device. The L30 flash memory device has two block
sizes: 16K-Word, and 64K-Word.
Main block: An array block that is usually used to store code and/or data. Main blocks are larger
than parameter blocks.
Parameter block: An array block that is usually used to store frequently changing data or small
system parameters that traditionally would be stored in EEPROM.
Top parameter device: Previously referred to as a top-boot device, a device with its parameter
partition located at the highest physical address of its memory map. Parameter blocks within a
www.DataSheet4U.comparameter partition are located at the highest physical address of the parameter partition.
Bottom parameter device: Previously referred to as a bottom-boot device, a device with its
parameter partition located at the lowest physical address of its memory map. Parameter blocks
within a parameter partition are located at the lowest physical address of the parameter partition.
Partition: A group of blocks that share common program/erase circuitry. Blocks within a partition
also share a common status register. If any block within a partition is being programmed or erased,
only status register data (rather than array data) is available when any address within that partition
is read.
Main partition: A partition containing only main blocks.
Parameter partition: A partition containing parameter blocks and main blocks.
Acronyms
CUI: Command User Interface
MLC: Multi-Level Cell
OTP: One-Time Programmable
PLR: Protection Lock Register
PR: Protection Register
RCR: Read Configuration Register
RFU: Reserved for Future Use
SR: Status Register
WSM: Write State Machine
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부품번호상세설명 및 기능제조사
GE28F640L30

Wireless Memory

Intel Corporation
Intel Corporation

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