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PDF CS43122 Data sheet ( Hoja de datos )

Número de pieza CS43122
Descripción 192kHz DAC for Digital Audio
Fabricantes Cirrus Logic 
Logotipo Cirrus Logic Logotipo



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CS43122
122 dB, 24-Bit, 192 kHz DAC for Digital Audio
Features
Description
l 24 Bit Conversion
l Up to 192 kHz Sample Rates
l 122 dB Dynamic Range
l -102 dB THD+N
l Second-Order Dynamic-Element Matching
l Low Clock Jitter Sensitivity
l 102 dB Stop-band attenuation
l Single +5 V supply
l Soft Mute Control
l Digital De-Emphasis for 32, 44.1, and 48 kHz
l External Reference Input
l Pin-compatible with the CS4396
The CS43122 is a complete high performance 24 bit-
192 kHz stereo digital-to-analog conversion system. The
device includes a digital interpolation filter followed by an
oversampled 5 bit delta-sigma modulator which drives
second generation dynamic-element-matching (DEM)
selection logic. The output from the DEM block controls
the input to a multi-element switched capacitor DAC/low-
pass filter, with fully-differential outputs. This multi-bit ar-
chitecture features significantly lower out-of-band noise
and jitter sensitivity than traditional 1-bit designs, and the
advanced second generation DEM guarantees low noise
and distortion at all signal levels.
The CS43122 is the optimal D/A converter solution for
any application that requires the highest performance
and best possible sound quality including high-end con-
sumer and professional audio products such as
Universal DVD players, A/V receivers, Outboard D/A
Converters, CD Players, and Mixing Consoles.
ORDERING INFORMATION
CS43122-KS -10° to 70° C 28-pin SOIC
CDB43122
Evaluation Board
SCLK
LRCK
SDATA
SERIAL INTERFACE
AND FORMAT SELECT
SOFT MUTE
DE-EMPHASIS
FILTER
MCLK
CLOCK
DIVIDER
INTERPOLATION
FILTER
MULTI-BIT
∆Σ
MODULATOR
INTERPOLATION
FILTER
MULTI-BIT
∆Σ
MODULATOR
HARDWARE MODE CONTROL
(CONTROL PORT)
DYNAMIC
ELEMENT
MATCHING
LOGIC
SWITCHED
CAPACITOR-DAC
AND FILTER
DYNAMIC
ELEMENT
MATCHING
LOGIC
SWITCHED
CAPACITOR-DAC
AND FILTER
VOLTAGE REFERENCE
AOUTL+
AOUTL-
AOUTR+
AOUTR-
M4 M3
M2 M1 M0 RESET MUTEC MUTE
(AD0/CS) (AD1/CDIN) (SCL/CCLK)
(SDA/CDOUT)
FILT+ VREF FILT- CMOUT
Advance Product Information
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
P.O. Box 17847, Austin, Texas 78760
(512) 445 7222 FAX: (512) 445 7581
http://www.cirrus.com
DataSheet4 U .com
Copyright © Cirrus Logic, Inc. 2000
(All Rights Reserved)
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DEC ‘00
DS526PP2
1
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CS43122 pdf
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CS43122
ANALOG CHARACTERISTICS (CONTINUED)
Parameter
Symbol
Dynamic Performance - Operational Mode 0 (Fs = 48 kHz)
Dynamic Range
24-Bit
16-Bit
(Note 2)
(Note 1)
unweighted
A-Weighted
unweighted
A-Weighted
Total Harmonic Distortion + Noise
24-Bit
16-Bit
(Note 2)
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
THD+N
Dynamic Performance - Operational Mode 1 (Fs = 96 kHz)
Dynamic Range
(Note 1)
24-Bit
unweighted
A-Weighted
40 kHz bandwidth
unweighted
16-Bit
unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise
24-Bit
16-Bit
(Note 2)
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
THD+N
Dynamic Performance - Operational Mode 2 (Fs = 192 kHz)
Dynamic Range
(Note 1)
24-Bit
unweighted
A-Weighted
40 kHz bandwidth
unweighted
16-Bit
unweighted
(Note 2) A-Weighted
Total Harmonic Distortion + Noise
24-Bit
16-Bit
(Note 2)
(Note 1)
0 dB
-20 dB
-60 dB
0 dB
-20 dB
-60 dB
THD+N
Min
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
TBD
TBD
TBD
-
-
-
-
-
-
-
-
Typ Max Unit
117
120
95
98
-100
-97
-55
-95
-75
-35
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
117
120
114
92
98
-100
-97
-55
-95
-75
-35
-
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
117
120
114
95
98
-100
-97
-55
-95
-75
-35
-
-
-
-
-
TBD
TBD
TBD
-
-
-
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
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CS43122 arduino
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CS43122
SWITCHING CHARACTERISTICS - CONTROL PORT
(TA = 25° C; VD = 5.25 V to 3.0 Volts; Inputs: logic 0 = AGND, logic 1 = VD, CL = 30 pF)
SPI Mode
Parameter
Symbol
Min
CCLK Clock Frequency
RST Rising Edge to CS Falling
CCLK Edge to CS Falling
CS High Time Between Transmissions
CS Falling to CCLK Edge
CCLK Low Time
CCLK High Time
CDIN to CCLK Rising Setup Time
CCLK Rising to DATA Hold Time
Rise Time of CCLK and CDIN
Fall Time of CCLK and CDIN
CCLK Falling to CDOUT valid
(Note 9)
(Note 10)
(Note 11)
(Note 11)
fsclk
tsrs
tspi
tcsh
tcss
tscl
tsch
tdsu
tdh
tr2
tf2
tov
-
500
500
1.0
20
66
66
40
15
-
-
45
Max
6
-
-
-
-
-
-
-
-
100
100
Unit
MHz
ns
ns
µs
ns
ns
ns
ns
ns
ns
ns
ns
Notes: 9. tspi only needed before first falling edge of CS after RST rising edge. tspi = 0 at all other times.
10. Data must be held for sufficient time to bridge the transition time of CCLK.
11. For FSCK < 1 MHz
RST
t srs
CS
CCLK
CDIN
t spi t css
t scl t sch
t r2 t f2
t dsu t dh
Figure 3. SPI Control Port Timing
t csh
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