PDF SI3220 Data sheet ( Hoja de datos )

Número de pieza	SI3220
Descripción	(SI3220 / SI3225) DUAL PROSLIC PROGRAMMABLE CMOS SLIC/CODEC
Fabricantes	Silicon Laboratories
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No Preview Available ! www.DataSheet4U.com Si3220/25 DUAL PROSLIC® PROGRAMMABLE CMOS SLIC/CODEC Features Performs all BORSCHT functions Ideal for applications up to 18 kft Internal balanced ringing to 65 Vrms (Si3220) External bulk ringer support (Si3225) Software-programmable parameters: Ringing frequency, amplitude, cadence, and waveshape (Si3220) Two-wire ac impedance Transhybrid balance DC current loop feed (18–45 mA) Loop closure and ring trip thresholds Ground key detect threshold Automatic switching of up to three battery supplies On-hook transmission Loop or ground start operation with smooth/abrupt polarity reversal Modem/fax tone detection DTMF generation/decoding Dual tone generators A-Law/µ-Law, linear PCM companding PCM and SPI bus digital interfaces with programmable interrupts GCI mode support 3.3 or 5 V operation GR-909 loop diagnostics Audio diagnostics with loopback 12 kHz/16 kHz pulse metering (Si3220) FSK caller ID generation Lead-free/RoHS-compliant Part Number Si3220 Si3225 Ringing Method Internal External Ringer Applications Digital loop carriers Central Office telephony Pair gain remote terminals Wireless local loop Private Branch Exchange (PBX) systems Cable telephony Voice over IP/voice over DSL ISDN terminal adapters Ordering Information See “Dual ProSLIC Selection Guide” on page 109. Description U.S. Patent #6,567,521 The Dual ProSLIC® is a series of low-voltage CMOS devices that integrate both SLIC and codec functionality into a single IC to provide a complete dual-channel analog telephone interface in accordance with all relevant LSSGR, ITU, and ETSI specifications. The Si3220 includes internal ringing generation to eliminate centralized ringers and ringing relays, and the Si3225 supports centralized ringing for long loop and legacy applications. On-chip subscriber loop and audio testing allows remote diagnostics and fault detection with no external test equipment or relays. The Si3220 and Si3225 operate from a single 3.3 or 5 V supply and interface to standard PCM/SPI or GCI bus digital interfaces. The Si3200 linefeed interface IC performs all high-voltage functions and operates from a 3.3 V or 5 V supply as well as single or dual battery supplies up to 100 V. The Si3220 and Si3225 are available in a 64-pin thin quad flat package (TQFP), and the Si3200 is available in a thermally-enhanced 16-pin small outline (SOIC) package. U.S. Patent #6,812,744 Other patents pending Functional Block Diagram CS SCLK SDO SDI DTX DRX FSYNC PCLK INT RESET SPI Control Interface PCM / GCI Interface PLL Si3220/25 Pulse Metering 2-Wire AC Impedance Subscriber Line Diagnostics Hybrid Balance Ringing Generator & Ring Trip Sense DTMF Decode DSP FSK Catellexrt ID Dual Tone Generators Modem Tone Detection Programmable Audio Filters Gain Adjust Loop Closure, & Ground Key Detection Relay Drivers Codec A DAC ADC Codec B DAC ADC SLIC A Linefeed Control Linefeed Monitor SLIC B Linefeed Control Linefeed Monitor Linefeed Interface TIP Channel A RING Linefeed Interface TIP Channel B RING Rev. 1.2 2/06 DataSheet4 U .com Copyright © 2006 by Silicon Laboratories www.DataSheet4U.com Si3220/25 www.DataSheet4U.com 1 page www.DataSheet4U.com Si3220/25 Table 2. Recommended Operating Conditions Parameter Symbol Test Min* Typ Max* Unit Condition Ambient Temperature Ambient Temperature TA K/F-Grade 0 25 70 oC TA B/G-Grade –40 25 85 oC Supply Voltage, Si3220/Si3225 VDD1–VDD4 3.13 3.3/5.0 5.25 V Supply Voltage, Si3200 High Battery Supply Voltage, Si3200 Low Battery Supply Voltage, Si3200 VDD VBATH VBATL 3.13 –15 –15 3.3/5.0 — — 5.25 –99 VBATH V V V *Note: All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. Typical values apply at nominal supply voltages and an operating temperature of 25 °C unless otherwise stated. Table 3. 3.3 V Power Supply Characteristics1 (VDD, VDD1 – VDD4 = 3.3 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Symbol Test Condition Min Typ Max Unit VDD1–VDD4 Supply Current (Si3220/ Si3225) IVDD1–IVDD4 Sleep mode, RESET = 0 Open (high-impedance) Active on-hook standby — 200 — µA — 17 — mA — 16 — mA Forward/reverse active off-hook — 45 + ILIM — + ABIAS mA Forward/reverse active OHT OBIAS = 4 mA, VBAT = –70 V — 47 — mA RingingS, VinReINWGa=ve4,51VRrmEsN, VlBoAaTd2= –70 V, — 26 — mA Notes: 1. All specifications are for a single channel based on measurements with both channels in the same operating state. 2. See "3.14.4. Ringing Power Considerations" on page 53 for current and power consumption under other operating conditions. 3. Power consumption does not include additional power required for dc loop feed. Total system power consumption must include an additional (VDD + \|VBAT\|) x ILOOP term. DataSheet4 U .com www.DatRaeSvh. 1e.2et4U.com 5 www.DataSheet4U.com 5 Page www.DataSheet4U.com Si3220/25 Table 5. AC Characteristics (Continued) (VDD, VDD1 – VDD4 = 3.13 to 5.25 V, TA = 0 to 70 °C for K/F-Grade, –40 to 85 °C for B/G-Grade) Parameter Test Condition Min Typ Max Unit Transhybrid Balance5 300 Hz to 3.4 kHz 34 40 — dB Idle Channel Noise6 PSRR from VDD1 – VDD4 PSRR from VBAT Longitudinal to Metallic/PCM Balance (forward or reverse) Metallic/PCM to Longitudinal Balance Longitudinal Impedance7 Noise Performance C-Message weighted Psophometric weighted 3 kHz flat RX and TX, dc to 3.4 kHz RX and TX, dc to 3.4 kHz Longitudinal Performance 200 Hz to 1 kHz 1 kHz to 3.4 kHz 200 Hz to 3.4 kHz 200 Hz to 3.4 kHz at TIP or RING Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA — — — 40 60 58 53 40 — — — — 12 15 dBrnC –78 –75 dBmP — 18 dBrn — — dB — — dB 70 — dB 58 — dB — — dB 50 — Ω 25 — Ω 25 — Ω 20 — Ω Longitudinal Current per Pin7 Active off-hook 200 Hz to 3.4 kHz Register-dependent OBIAS/ABIAS 00 = 4 mA 01 = 8 mA 10 = 12 mA 11 = 16 mA — 4 — mA — 8 — mA — 8 — mA — 10 — mA Notes: 1. The input signal level should be 0 dBm0 for frequencies greater than 100 Hz. For 100 Hz and below, the level should be –10 dBm0. The output signal magnitude at any other frequency will be smaller than the maximum value specified. 2. Analog signal measured as VTIP – VRING. Assumes ideal line impedance matching. 3. The quantization errors inherent in the µ/A-law companding process can generate slightly worse gain tracking performance in the signal range of 3 to –37 dB for signal frequencies that are integer divisors of the 8 kHz PCM sampling rate. 4. The digital gain block is a linear multiplier that is programmable from –∞ to +6 dB. The step size in dB varies over the complete range. See "3.25. Audio Path Processing" on page 69. 5. VDD1 – VDD4 = 3.3 V, VBAT = –52 V, no fuse resistors, RL = 600 Ω, ZS = 600 Ω synthesized using RS register coefficients. 6. The level of any unwanted tones within the bandwidth of 0 to 4 kHz does not exceed –55 dBm. 7. The OBIAS and ABIAS registers program the dc bias current through the SLIC in the on-hook transmission and off- hook active conditions, respectively. This per-pin total current setting should be selected so it can accommodate the sum of the metallic and longitudinal currents through each of the TIP and RING leads for a given application. DataSheet4 U .com www.DatRaeSvh. 1e.2et4U.com 11 www.DataSheet4U.com 11 Page

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