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PDF RJ80530VY400256 Data sheet ( Hoja de datos )
| Número de pieza | RJ80530VY400256 | |
| Descripción | Processor | |
| Fabricantes | Intel | |
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Ultra-Low Voltage Intel® Celeron®
Processor (0.13 µ) in the Micro FC-BGA
Package
at 650 MHz and 400 MHz
Datasheet
Product Features
■ Ultra-Low Voltage Intel® Celeron®
Processor (0.13µ) with the following
processor core/bus speeds:
— 650/100 MHz at 1.10 V
— 400/100 MHz at 0.95 V
■ Supports the Intel Architecture with
Dynamic Execution
■ On-die primary 16-Kbyte instruction cache
and 16-Kbyte write-back data cache
■ On-die second level cache (256-Kbyte)
with Advanced Transfer Cache
Architecture
■ Data Prefetch Logic
■ Integrated AGTL termination
■ Integrated math co-processor
■ Micro-FCBGA packaging technologies
— Supports small form factor applied
computing designs
— Exposed die enables more efficient heat
dissipation
■ Fully compatible with previous Intel
microprocessors
— Binary compatible with all applications
— Support for MMX™ technology
— Support for Streaming SIMD Extensions
■ Power Management Features
— Quick Start and Deep Sleep modes
provide low power dissipation
■ On-die thermal diode
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Order Number: 273804-002
May 2003
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Contents
8.1.31 LINT[1:0] (I - 1.5 V Tolerant) .................................................................................. 74
8.1.32 LOCK# (I/O - AGTL) .............................................................................................. 75
8.1.33 NCTRL (I - Analog) ................................................................................................ 75
8.1.34 NMI (I - 1.5 V Tolerant) ..........................................................................................75
8.1.35 PICCLK (I – 2.0 V Tolerant) ................................................................................... 75
8.1.36 PICD[1:0] (I/O - 1.5 V Tolerant Open-drain) .......................................................... 75
8.1.37 PLL1, PLL2 (Analog) ............................................................................................. 75
8.1.38 PRDY# (O - AGTL) ................................................................................................ 76
8.1.39 PREQ# (I - 1.5 V Tolerant) .................................................................................... 76
8.1.40 PWRGOOD (I – 1.8 V Tolerant)............................................................................. 76
8.1.41 REQ[4:0]# (I/O - AGTL) ......................................................................................... 76
8.1.42 RESET# (I - AGTL) ................................................................................................ 76
8.1.43 RP# (I/O - AGTL) ................................................................................................... 77
8.1.44 RS[2:0]# (I/O - AGTL) ............................................................................................77
8.1.45 RSP# (I - AGTL) .................................................................................................... 77
8.1.46 RTTIMPEDP (I-Analog) ......................................................................................... 77
8.1.47 SMI# (I - 1.5 V Tolerant) ........................................................................................ 77
8.1.48 STPCLK# (I - 1.5 V Tolerant)................................................................................. 77
8.1.49 TCK (I - 1.5 V Tolerant) ......................................................................................... 78
8.1.50 TDI (I - 1.5 V Tolerant) ........................................................................................... 78
8.1.51 TDO (O - 1.5 V Tolerant Open-drain) .................................................................... 78
8.1.52 TESTHI[2:1] (I - 1.25 V Tolerant) ........................................................................... 78
8.1.53 TESTLO[2:1] (I - 1.5 V Tolerant)............................................................................ 78
8.1.54 THERMDA, THERMDC (Analog)........................................................................... 78
8.1.55 TMS (I - 1.5 V Tolerant) ......................................................................................... 78
8.1.56 TRDY# (I/O - AGTL) .............................................................................................. 78
8.1.57 TRST# (I - 1.5 V Tolerant) .....................................................................................78
8.1.58 VID[4:0] (O – Open-drain)...................................................................................... 79
8.1.59 VREF (Analog) ........................................................................................................79
8.1.60 VTTPWRGD (I – 1.25 V) ....................................................................................... 79
8.2 Signal Summaries...............................................................................................................79
Figures
1 Clock Control States ................................................................................................................... 15
2 PLL RLC Filter ............................................................................................................................ 23
3 PLL Filter Specifications ............................................................................................................. 24
4 VTTPWRGD System-Level Connections ................................................................................... 27
5 Noise Estimation ......................................................................................................................... 28
6 BCLK (Single Ended)/PICCLK/TCK Generic Clock Timing Waveform....................................... 39
7 Differential BCLK/BCLK# Waveform (Common Mode) .............................................................. 39
8 BCLK/BCLK# Waveform (Differential Mode) ..............................................................................40
9 Valid Delay Timings ....................................................................................................................40
10 Setup and Hold Timings ............................................................................................................. 40
11 Cold/Warm Reset and Configuration Timings ............................................................................ 41
12 Power-on Sequence and Reset Timings .................................................................................... 42
13 Power Down Sequencing and Timings (VCC Leading) ............................................................... 43
14 Power Down Sequencing and Timings (VCCT Leading)............................................................ 44
15 Test Timings (Boundary Scan) ................................................................................................... 45
Datasheet
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Ultra-Low Voltage Intel® Celeron® Processor — 650 MHz and 400 MHz
• Intel® Mobile Voltage Positioning -II (IMVP-II) Design Guide (Contact your Intel Field Sales
Representative)
• Mobile Intel® Pentium® III Processor-M /440MX Platform Design Guide (Contact your Intel
Field Sales Representative)
• Intel Processor Identification and the CPUID Instruction Application Note AP-485 (241618)
Datasheet
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