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PDF BT8110B Data sheet ( Hoja de datos )
| Número de pieza | BT8110B | |
| Descripción | High-Capacity ADPCM Processor | |
| Fabricantes | ETC | |
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Bt8110/8110B
High-Capacity ADPCM Processor
This specification describes the Bt8110 and Bt8110B multichannel ADPCM processor
CMOS integrated circuits that implement Adaptive Differential Pulse-Code Modulation
(ADPCM) encoding and decoding. The fixed-rate coding algorithms include those
specified in ANSI Standard T1.303-1989. These algorithms are identical to those in
ITU-T Recommendations G.726 and G.727. These circuits also implement the
variable-rate or embedded codes specified in ANSI Standard T1.310-1991 and ITU-T
Recommendation G.727.
A single ADPCM processor integrated circuit can provide 24 or 32 full-duplex
channels of ADPCM processing (encoding and decoding). In some applications, two
circuits can be combined to provide 48 or 64 full-duplex channels. Both A-law and µ-law
PCM translations are provided.
Interface options such as serial and parallel inputs and outputs, along with hardware
and microprocessor control modes, are provided by the integrated circuits. Up to 14
separate ADPCM algorithms are available in any given configuration on a per-channel
basis.
The Bt8110 requires an external lookup table ROM. The Bt8110B has an internal
lookup table ROM, or can use an external lookup table ROM. When in direct framer
interface mode, transparent channels in the Bt8110 will operate at 56 kbit/s; the
Bt8110B operates
been added to the
Batt86141k0bBi.t/Fso. rAmhoarrdewdaerteailcsoonntrothl,edDBirate8tca1tS1f0rhaBememetro4diUnet.eccroofnamctreomls,ordeefehratso
Table 1-1 and Table 1-4.
Distinguishing Features
• Bt8110B offers internal ROM
• 24 or 32 full-duplex channel capacity
(48 or 64 channels with two
processors)
• 2-, 3-, 4- and 5-bit quantization
dynamically selectable on a
channel-by-channel, frame-by-frame
basis
• Transparent channel operation
• Two control modes available:
microprocessor and hardware.
• Direct framer interface for both T1
and E1 signal formats
• Supports the optimal RESET function
described in the algorithm standards
• Supports even-bit inversion of A-law
inputs and outputs (required by
ITU-T Recommendations G.726, and
G.727)
• Minimum throughput delay
• Pin compatible with Bt8110
• 8 mw per-channel, low-power CMOS
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Functional Block Diagram
64 Kbit/s
PCM
Input
32 Kbit/s
ADPCM
Input
Convert to
Uniform
PCM
ENCODER
Input
Difference
+Signal
+
Signal
– Signal
Estimate
Adaptive
Quantizer
Reconstructed
Signal
Adaptive
Predictor
+
Quantized
Inverse
Adaptive
Quantizer
Difference Signal
Quantized
+Difference
Inverse Signal
Adaptive
Quantizer
+
–
Reconstructed
Signal Convert to
PCM
DECODER
Signal
Estimate
Synchronous
Coding
Adjustment
Adaptive
Predictor
32 Kbit/s
ADPCM
Output
Applicable Standards
• ANSI T1.302-1987
• ANSI T1.303-1989
• ANSI T1.310-1991
• ITU-T G.726, G.727
• ANSI T1.501-1994
• ANSI T1Y1 Technical Reports #3 and
#10
64 Kbit/s
PCM
Output
Applications
• T1/E1 Transcoders
• T1/E1 Multiplexers
• Personal Communications Systems:
Digital European Cordless
Telecommunications (DECT),
Personal Access Communications
System (PACS)
• Wireless Local Loop
• Voice PairGain
• DCME Systems
• Speech Processing/Recording
• Voice Mail/Packetization
• Voice over ATM/Frame Relay
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Data Sheet
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100060C
January 2000
1 page  
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Bt8110/8110B
High-Capacity ADPCM Processor
List of Figures
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List of Figures
Figure 1-1.
Figure 1-2.
Figure 1-3.
Figure 1-4.
Figure 2-1.
Figure 2-2.
Figure 2-3.
Figure 2-4.
Figure 2-5.
Figure 2-6.
Figure 2-7.
Figure 2-8.
Figure 4-1.
Figure 4-2.
Figure 4-3.
Figure A-1.
Figure A-2.
Figure A-3.
Figure A-4.
Figure B-1.
Figure B-2.
Figure C-1.
Figure C-2.
Figure D-1.
Figure D-2.
Figure E-1.
Figure E-2.
Bt8110 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Bt8110 Logic Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Bt8110B Pinout Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7
Bt8110B Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9
Bt8110 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Bt8110B Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Input and Output Timing for 24- or 32-Channel Full-Duplex
Interleaved Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6
Input and Output Timing for 48- or 64-Channel Half-Duplex
Encoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Input and Output Timing for 48- or 64-Channel Half-Duplex
Decoder-Only Operation (Microprocessor Control) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10
Hardware Control Interleaved Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15
Hardware Control Encoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-16
Hardware Control Decoder-Only Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17
Microprocessor Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
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Input and Output Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3
68-Pin Plastic Leaded Chip Carrier (J-Bend) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7
48- or 64-Channel Configuration of the Bt8110/8110B . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-2
48- or 64-Channel Full-Duplex Interleaved Mode Functional Timing . . . . . . . . . . . . . . . . . . A-3
96- or 128-Channel Half-Duplex Encoder-Only Functional Timing. . . . . . . . . . . . . . . . . . . . A-4
96- or 128-Channel Half-Duplex Decoder-Only Functional Timing . . . . . . . . . . . . . . . . . . . A-5
T1 Speech Compression Interface Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-2
T1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-4
E1 Speech Compression Interface Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-2
E1 Speech Compression Functional Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-4
Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-2
Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . D-3
Single-Board Transcoder Assembly. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-2
Single-Board Transcoder Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . E-3
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Bt8110/8110B
High-Capacity ADPCM Processor
1.0 Product Description
1.1 Channel Capacity and Configuration Modes
1.1.2 Embedded Coding
The Bt8110/8110B has the capability to provide embedded coding according to
ANSI Standard T1.310-1991 and ITU-T Recommendation G.727. This coding
technique allows the encoding to be performed with 5 bits of encoding
information, and the decoding to be done with anywhere from 2 to 5 input bits.
The coding algorithm is defined so that although the coding distortion increases
as the number of bits at the decoder decreases, the encoder and the decoder will
remain synchronized.
The Bt8110/8110B is designed so that embedded coding is enabled by the
ROM code selected. Along with four different standard (non-embedded) ADPCM
codes, two embedded codes can be provided with a 64 K ROM and up to six
different embedded codes, with eight different standard (non-embedded) codes,
can be provided with a 128 K ROM. The encoder always provides the maximum
number of bits (up to 5) defined by the code selected. The decoder requires up to
5 ADPCM bits and a 2-bit encoded input that indicates how many bits are present
at the decoder input. This input signal is applied to bits 1 and 2 of the parallel
input bus. If embedded coding is not in use, bits 1 and 2 should be connected to
ground.
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1.1.3 Control Mode
Each channel has four sets of per-channel control inputs. These are for selecting
the PCM coding law (A-law or µ-law), selecting transparent operation, selecting
the RESET function of the ADPCM coding algorithm, and selecting which of 14
codes (six codesDfaotraaS6h4eeKt4RUO.cMo)mis used for encoding or decoding.
The microprocessor mode is selected by setting input MICREN high. The
microprocessor can address 65 different registers. There is a control register for
each of the encoder and decoder channel operations and a mode control register
that sets the operating mode of the Bt8110/8110B.
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