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T8207 데이터시트 PDF




Agere Systems에서 제조한 전자 부품 T8207은 전자 산업 및 응용 분야에서
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기능 ATM Interconnect
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T8207 데이터시트, 핀배열, 회로
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Advance Data Sheet
September 2001
CelXpresT8207
ATM Interconnect
1 Product Overview
1.1 Features
s Programmable priority for control/data cells trans-
mission onto cell bus
s Eight GPIO pins
s > OC-3 transport capability
s JTAG support
s UTOPIA level 1 and 2 (8-bit) cell-level handshake
s Optional monitoring of misrouted cells
interface (ATM or PHY layers)
s 32 multi-PHY (MPHY) operation
s Microprocessor interface, supporting both Motor-
ola® and Intel® modes (multiplexed and nonmulti-
plexed)
s Shared UTOPIA mode
s Control cell transmission and reception through
s Egress SDRAM buffer support to expand UTOPIA
microprocessor port
output priority queues for 32K to 512K cells:
— 64 queues configurable up to four queues per
s Single 3.3 V power supply
PHY with programmable sizes
s 3.3 V TTL I/O (5 V tolerant)
— Programmable number of UTOPIA output
queues with four levels of priority
s 272-pin PBGA package
s Support of ATM traffic management via partial
s Industrial temperature range (–40 °C to +85 °C)
packet discard (PPD), forward explicit DcoantagSehsetioent4U.coms Hot insertion capability
DataShee
notification (FECN), and the cell loss priority (CLP)
bit
s Compatible with Transwitch CellBus®
s Programmable slew rate GTL+ I/O:
— 1.7 Gbits/s cell bus operation
— Programmable as bus arbiter
s Flexible per port cell counters
s Cell header translation and insertion with virtual
path identifier (VPI) and virtual channel identifier
(VCI) via external SRAM (up to 64K entries)
1.2 Applications
s Asymmetric digital subscriber line (ADSL) digital
subscriber line access multiplexer (DSLAMs)
s Access gateways
s Access multiplexers/concentrators
s Support of network node interface (NNI) and user
network interface (UNI) header types with optional
generic flow control (GFC) insertion
s Multiservice access equipment platforms
s Programmable operations and maintenance and
resource management (OAM/RM) cell routing
s Support of multicast and broadcast cells per PHY
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T8207 pdf, 반도체, 판매, 대치품
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CelXpres T8207
ATM Interconnect
Advance Data Sheet
September 2001
Table of Contents (continued)
Figure
Page
Figure 1. Functional Block Diagram ......................................................................................................................... 9
Figure 2. Dual Bus Implementation ........................................................................................................................ 10
Figure 3. 272-Pin PBGA—Top View ...................................................................................................................... 19
Figure 4. Translation RAM Memory Map—8-Byte Records, for Up to 16 Ports ..................................................... 29
Figure 5. Translation RAM Memory Map—8-Byte Records, for Greater than 16 Ports...........................................30
Figure 6. Translation Record Types—8-Byte Records........................................................................................... 31
Figure 7. Translation RAM Flow Diagram .............................................................................................................. 35
Figure 8. Translation Record Types—Extended Mode .......................................................................................... 37
Figure 9. Translation RAM Memory Map—Extended Mode, for Up to 16 Ports..................................................... 38
Figure 10. Translation RAM Memory Map—Extended Mode, for Greater than 16 Ports ........................................39
Figure 11. Queue Priority Multiplexing ................................................................................................................... 46
Figure 12. TX UTOPIA Cell Handling ..................................................................................................................... 47
Figure 13. TX UTOPIA Bus Sharing....................................................................................................................... 49
Figure 14. Cell Bus Frame Format (Bit Positions for 16 User Mode) ..................................................................... 56
Figure 15. Cell Bus Frame Format (Bit Positions for 32 User Mode) ..................................................................... 57
Figure 16. Cell Bus Routing Headers ..................................................................................................................... 59
Figure 17. GTL+ External Circuitry ......................................................................................................................... 62
Figure 18. SDRAM Timing Parameters .................................................................................................................. 65
Figure 19. Crystal ................................................................................................................................................. 143
Figure 20. Negative Resistance Plot .................................................................................................................... 143
et4U.comFigure 21. Nonmultiplexed Intel Mode Write Access Timing ................................................................................ 146
Figure 22. Nonmultiplexed Intel Mode Read Access Timing................................................................................ 146
Figure 23. Motorola Mode Write Access Timing........D..a..t..a..S..h..e..e..t.4..U....c.o..m................................................................. 148
Figure 24. Motorola Mode Read Access Timing .................................................................................................. 148
Figure 25. Multiplexed Intel Mode Write Access Timing....................................................................................... 150
Figure 26. Multiplexed Intel Mode Read Access Timing ...................................................................................... 150
Figure 27. External LUT Memory Read Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 28. External LUT Memory Write Timing (cyc_per_acc = 2 and cyc_per_acc = 3) .................................... 153
Figure 29. Cell Bus Timing ................................................................................................................................... 155
Figure 30. SDRAM Interface Timing..................................................................................................................... 156
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T8207 전자부품, 판매, 대치품
www.DataSheet4U.com
Advance Data Sheet
September 2001
CelXpres T8207
ATM Interconnect
Table of Contents (continued)
Table
Page
et4U.com
Table 100. PPD Memory Write (PPDMW) (0418h) ............................................................................................. 124
Table 101. PHY Port X Transmit Count Structure (PPXTXCNT) (0600h to 067Ch) ............................................ 125
Table 102. PHY Port X Receive Count Structure (PPXRXCNT) (0700h to 07F8h) ............................................. 126
Table 103. LUT X Configuration 1 Structure (LUTXCF1) (0704h to 077Ch)......................................................... 127
Table 104. SDRAM Control (SCT) (0400h) ......................................................................................................... 128
Table 105. SDRAM Interrupt Status (SIS) (0402h) ............................................................................................. 128
Table 106. SDRAM Interrupt Enable (SIE) (0404h) ............................................................................................ 128
Table 107. SDRAM Configuration (SCF) (0408h) ............................................................................................... 129
Table 108. Refresh (RFRSH) (0410h) ................................................................................................................ 130
Table 109. Refresh Lateness (RFRSHL) (0412h) ............................................................................................... 130
Table 110. Idle State 1 (IS1) (0420h) .................................................................................................................. 130
Table 111. Idle State 2 (IS2) (0422h) .................................................................................................................. 130
Table 112. Manual Access State 1 (MAS1) (0424h) ........................................................................................... 131
Table 113. Manual Access State 2 (MAS2) (0426h) ........................................................................................... 131
Table 114. SDRAM Interrupt Service Request 4 (SISR4) (0438h) ........................................................................ 132
Table 115. SDRAM Interrupt Service Request 3 (SISR3) (043Ah)........................................................................ 132
Table 116. SDRAM Interrupt Service Request 1 (SISR1) (043Ch) ..................................................................... 132
Table 117. SDRAM Interrupt Service Request 2 (SISR2) (043Eh) ..................................................................... 132
Table 118. Queue X (QX) (0440h to 04BEh) ....................................................................................................... 133
Table 119. Queue X Definition Structure (QXDEF) (2000h to 27E0h) ................................................................. 135
Table 120. Control Cell Receive Extended Memory (CCRXEM) (0800h to 0832h) ............................................. 137DataShee
Table 121. Control Cell Transmit Extended Memory (CCTXEM) (0900h to 0936h) ............................................ 137
Table 122. PHY Port 0 and Control Cells MuDltaictaSsthEexette4nUd.ceodmMemory (PP0MEM) (0C00h to 0C1Eh)............... 138
Table 123. PHY Port X Multicast Memory (PPXMM) (0C20h to 0DE0h) ............................................................. 139
Table 124. PPD Memory (PPDM) (1000h to 13FEh) .......................................................................................... 140
Table 125. Translation RAM Memory (TRAM) (100000h to 17FFFEh) ............................................................... 141
Table 126. SDRAM (SDRAM) (2000000h to 3FFFFFEh) ................................................................................... 141
Table 127. Maximum Rating Parameters and Values.......................................................................................... 142
Table 128. Recommended Operating Conditions ................................................................................................ 142
Table 129. HBM ESD Threshold .......................................................................................................................... 142
Table 130. Crystal Specifications ........................................................................................................................ 143
Table 131. External Clock Requirements............................................................................................................. 143
Table 132. dc Electrical Characteristics .............................................................................................................. 144
Table 133. Input Clocks ...................................................................................................................................... 145
Table 134. Output Clocks .................................................................................................................................... 145
Table 135. Nonmultiplexed Intel Mode Write Access Timing .............................................................................. 147
Table 136. Nonmultiplexed Intel Mode Read Access Timing .............................................................................. 147
Table 137. Motorola Mode Write Access Timing ................................................................................................. 149
Table 138. Motorola Mode Read Access Timing ................................................................................................. 149
Table 139. Multiplexed Intel Mode Write Access Timing .................................................................................... 151
Table 140. Multiplexed Intel Mode Read Access Timing ..................................................................................... 151
Table 141. TX UTOPIA Timing (70 pF Load on Outputs) ................................................................................... 152
Table 142. RX UTOPIA Timing (70 pF Load on Outputs) ................................................................................... 152
Table 143. External LUT Memory Read Timing (cyc_per_acc = 2) .................................................................... 154
Table 144. External LUT Memory Read Timing (cyc_per_acc = 3) .................................................................... 154
Table 145. External LUT Memory Write Timing (cyc_per_acc = 2) .................................................................... 154
Table 146. External LUT Memory Write Timing (cyc_per_acc = 3) .................................................................... 154
Table 147. Cell Bus Timing ................................................................................................................................. 155
Table 148. SDRAM Interface Timing .................................................................................................................. 156
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